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? 1998-2013 microchip technology inc. ds30605d-page 1 pic16c63a/65b/73b/74b devices included in this data sheet: pic16cxx microcontroller core features: ? high performance risc cpu ? only 35 single word instructions to learn ? all single cycle instructions except for program branches which are two cycle ? operating speed: dc - 20 mhz clock input dc - 200 ns instruction cycle ? 4 k x 14 words of program memory, 192 x 8 bytes of data memory (ram) ? interrupt capability ? eight-level deep hardware stack ? direct, indirect and relative addressing modes ? power-on reset (por) ? power-up timer (pwrt) and oscillator start-up timer (ost) ? watchdog timer (wdt) with its own on-chip rc oscillator for reliable operation ? programmable code protection ? power-saving sleep mode ? selectable oscillator options ? low power, high speed cmos eprom technology ? wide operating voltage range: 2.5v to 5.5v ? high sink/source current 25/25 ma ? commercial, industrial and automotive temperature ranges ? low power consumption: - < 5 ma @ 5v, 4 mhz -23 ? a typical @ 3v, 32 khz -< 1.2 ? a typical standby current pic16c7x peripheral features: ? timer0: 8-bit timer/counter with 8-bit prescaler ? timer1: 16-bit timer/counter with prescaler can be incremented during sleep via external crystal/clock ? timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler ? capture, compare, pwm modules - capture is 16-bit, max. resolution is 200 ns - compare is 16-bit, max. resolution is 200 ns - pwm max. resolution is 10-bit ? 8-bit multichannel analog-to-digital converter ? synchronous serial port (ssp) with spi tm and i 2 c tm ? universal synchronous asynchronous receiver transmitter (usart/sci) ? parallel slave port (psp), 8-bits wide with external rd , wr and cs controls ? brown-out detection circuitry for brown-out reset (bor) pin diagram: ? pic16c63a ? pic16c73b ? pic16c65b ? pic16c74b devices i/o pins a/d chan. psp interrupts pic16c63a 22 - no 10 pic16c65b 33 - yes 11 pic16c73b 22 5 no 11 pic16c74b 33 8 yes 12 pdip, windowed cerdip rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0/int v dd v ss rd7/psp7 rd6/psp6 rd5/psp5 rd4/psp4 rc7/rx/dt rc6/tx/ck rc5/sdo rc4/sdi/sda rd3/psp3 rd2/psp2 mclr /v pp ra0/an0 ra1/an1 ra2/an2 ra3/an3/v ref ra4/t0cki ra5/ss /an4 re0/rd /an5 re1/wr /an6 re2/cs /an7 v dd v ss osc1/clkin osc2/clkout rc0/t1oso/t1cki rc1/t1osi/ccp2 rc2/ccp1 rc3/sck/scl rd0/psp0 rd1/psp1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 pic16c65b pic16c74b 8-bit cmos microcontrolle rs with a/d converter
pic16c63a/65b/73b/74b ds30605d-page 2 ? 1998-2013 microchip technology inc. mclr /v pp ra0/an0 ra1/an1 ra2/an2 ra3/an3/v ref ra4/t0cki ra5/ss/an4 v ss osc1/clkin osc2/clkout rc0/t1oso/t1cki rc1/t1osi/ccp2 rc2/ccp1 rc3/sck/scl rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0/int v dd v ss rc7/rx/dt rc6/tx/ck rc5/sdo rc4/sdi/sda ? 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 sdip, soic, windowed cerdip rb3 rb2 rb1 rb0/int v dd v ss rd7/psp7 rd6/psp6 rd5/psp5 rd4/psp4 rc7/rx/dt ra4/t0cki ra5/ss/an4 re0/rd/an5 re1/wr/an6 re2/cs/an7 v dd v ss osc1/clkin osc2/clkout rc0/t1oso/t1cki nc ra3/an3/v ref ra2/an2 ra1/an1 ra0/an0 mclr /v pp nc rb7 rb6 rb5 rb4 nc 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 nc rc6/tx/ck rc5/sdo rc4/sdi/sda rd3/psp3 rd2/psp2 rd1/psp1 rd0/psp0 rc3/sck/scl rc2/ccp1 6 5 4 3 2 1 44 43 42 41 40 28 27 26 25 24 23 22 21 20 19 18 pic16c65b nc rc0/t1oso/t1cki osc2/clkout osc1/clkin v ss v dd re2/cs/an7 re1/wr/an6 re0/rd/an5 ra5/ss/an4 ra4/t0cki rc7/rx/dt rd4/psp4 rd5/psp5 rd6/psp6 rd7/psp7 v ss v dd rb0/int rb1 rb2 rb3 rc6/tx/ck rc5/sdo rc4/sdi/sda rd3/psp3 rd2/psp2 rd1/psp1 rd0/psp0 rc3/sck/scl rc2/ccp1 rc1/t1osi/ccp2 nc 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 ra3/an3/v ref ra2/an2 ra1/an1 ra0/an0 mclr /v pp rb7 rb6 rb5 rb4 nc nc 44 43 42 41 40 39 38 37 36 35 34 22 21 20 19 18 17 16 15 14 13 12 mqfp plcc pic16c74b tqfp rc1/t1osi/ccp2 pic16c65b pic16c74b pic16c63a pic16c73b key features pic ? mid-range mcu family reference manual (ds33023) pic16c63a pic16c65b pic16c73b pic16c74b program memory (eprom) x 14 4 k 4 k 4 k 4 k data memory (bytes) x 8 192 192 192 192 pins 28 40 28 40 parallel slave port ? yes ? yes capture/compare/pwm modules 2 2 2 2 timer modules 3 3 3 3 a/d channels ? ? 5 8 serial communication spi/i 2 c, usart spi/i 2 c, usart spi/i 2 c, usart spi/i 2 c, usart in-circuit serial programming yes yes yes yes brown-out reset yes yes yes yes interrupt sources 10 11 11 12 packages 28-pin sdip, soic, ssop, windowed cerdip 40-pin pdip; 44-pin plcc, mqfp, tqfp, windowed cerdip 28-pin sdip, soic, ssop, windowed cerdip 40-pin pdip; 44-pin plcc, mqfp, tqfp, windowed cerdip
? 1998-2013 microchip technology inc. ds30605d-page 3 pic16c63a/65b/73b/74b table of contents 1.0 general description......................................................................................................... ............................................................. 5 2.0 pic16c63a/65b/73b/74b device varieties ...................................................................................... ........................................... 7 3.0 architectural overview ...................................................................................................... ........................................................... 9 4.0 memory organization ......................................................................................................... ........................................................ 15 5.0 i/o ports ................................................................................................................... .................................................................. 29 6.0 timer0 module ............................................................................................................... ............................................................ 39 7.0 timer1 module ............................................................................................................... ............................................................ 43 8.0 timer2 module ............................................................................................................... ............................................................ 47 9.0 capture/compare/pwm modules ................................................................................................. ............................................. 49 10.0 synchronous serial port (ssp) module ....................................................................................... .............................................. 55 11.0 addressable universal synchronous asynchr onous receiver transmitter (usart)................................................ ................ 65 12.0 analog-to-digital converter (a/d) module .................................................................................. ............................................... 79 13.0 special features of the cpu................................................................................................ ...................................................... 85 14.0 instruction set summary .................................................................................................... ........................................................ 99 15.0 development support........................................................................................................ ....................................................... 107 16.0 electrical characteristics ................................................................................................. ......................................................... 113 17.0 dc and ac characteristics graphs and tables................................................................................ ....................................... 139 18.0 packaging information...................................................................................................... ........................................................ 153 appendix a: revision history ................................................................................................... ..................................................... 165 appendix b: device differences.................................................................................................. ................................................... 165 appendix c: device migrations - pic16c63/65a/73a/74a ? pic16c63a/65b/73b/74b ............................................................. 166 appendix d: migration from baseline to mid-range devices........................................................................ ................................. 168 on-line support................................................................................................................ ................................................................. 175 reader response ................................................................................................................ .............................................................. 176 product identification system .................................................................................................. .......................................................... 177 to our valued customers it is our intention to provide our valued customers with the best documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regar ding this publication, please contact the marketing communications department via e-mail at docerrors@mail.microchip.com or fax the reader response form in the back of this data sheet to (480) 792-4150. we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the vers ion number, (e.g., ds30000a is version a of document ds30000). errata an errata sheet, describing minor operational differences fr om the data sheet and recommended workarounds, may exist for curren t devices. as device/documentation issues become known to us, we will publish an errata sheet. the errata will specify the revisi on of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particular device, please check with one of the following: ? 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pic16c63a/65b/73b/74b ds30605d-page 4 ? 1998-2013 microchip technology inc. notes:
? 1998-2013 microchip technology inc. ds30605d-page 5 pic16c63a/65b/73b/74b 1.0 general description the pic16c63a/65b/73b/74b devices are low cost, high performance, cmos, fully-static, 8-bit micro- controllers in the pic16cxx mid-range family. all pic ? microcontrollers employ an advanced risc architecture. the pic16cxx microcontroller family has enhanced core features, eight-level deep stack and multiple internal and external interrupt sources. the separate instruction and data buses of the harvard architecture allow a 14-bit wide instruction word with the separate 8-bit wide data. the two stage instruction pipeline allows all instructions to execute in a single cycle, except for program branches, which require two cycles. a total of 35 instructions (reduced instruction set) are available. additionally, a large register set gives some of the architectural innovations used to achieve a very high performance. the pic16c63a/73b devices have 22 i/o pins. the pic16c65b/74b devices have 33 i/o pins. each device has 192 bytes of ram. in addition, several peripheral features are available, including: three timer/ counters, two capture/compare/pwm modules, and two serial ports. the synchronous serial port (ssp) can be configured as either a 3-wire serial peripheral interface (spi) or the two-wire inter-integrated circuit (i 2 c) bus. the universal synchronous asynchronous receiver transmitter (usart) is also known as the serial communications interface or sci. also, a 5- channel high speed 8-bit a/d is provided on the pic16c73b, while the pic16c74b offers 8 channels. the 8-bit resolution is ideally suited for applications requiring low cost analog interface, e.g., thermostat control, pressure sensing, etc. the pic16c63a/65b/73b/74b devices have special features to reduce external components, thus reducing cost, enhancing system reliability and reducing power consumption. there are four oscillator options, of which the single pin rc oscillator provides a low cost solution, the lp oscillator minimizes power consumption, xt is a standard crystal, and the hs is for high speed crys- tals. the sleep (power-down) feature provides a power-saving mode. the user can wake-up the chip from sleep through several external and internal interrupts and resets. a highly reliable watchdog timer (wdt), with its own on-chip rc oscillator, provides protection against soft- ware lockup, and also provides one way of waking the device from sleep. a uv erasable cerdip packaged version is ideal for code development, while the cost effective one-time- programmable (otp) version is suitable for production in any volume. the pic16c63a/65b/73b/74b devices fit nicely in many applications ranging from security and remote sensors to appliance control and automotive. the eprom technology makes customization of applica- tion programs (transmitter codes, motor speeds, receiver frequencies, etc.) extremely fast and con- venient. the small footprint packages make this micro- controller series perfect for all applications with space limitations. low cost, low power, high performance, ease of use and i/o flexibility make the pic16c63a/ 65b/73b/74b devices very versatile, even in areas where no microcontroller use has been considered before (e.g., timer functions, serial communication, capture and compare, pwm functions and coprocessor applications). 1.1 family and upward compatibility users familiar with the pic16c5x microcontroller fam- ily will realize that this is an enhanced version of the pic16c5x architecture. please refer to appendix a for a detailed list of enhancements. code written for the pic16c5x can be easily ported to the pic16cxx fam- ily of devices (appendix b). 1.2 development support pic ? devices are supported by the complete line of microchip development tools. please refer to section 15.0 for more details about microchip?s development tools.
pic16c63a/65b/73b/74b ds30605d-page 6 ? 1998-2013 microchip technology inc. notes:
? 1998-2013 microchip technology inc. ds30605d-page 7 pic16c63a/65b/73b/74b 2.0 pic16c63a/65b/73b/74b device varieties a variety of frequency ranges and packaging options are available. depending on application and production requirements, the proper device option can be selected using the information in the pic16c63a/65b/73b/74b product identification system section at the end of this data sheet. when placing orders, please use that page of the data sheet to specify the correct part number. for the pic16c7x family, there are two device ?types? as indicated in the device number: 1. c , as in pic16 c 74. these devices have eprom type memory and operate over the standard voltage range. 2. lc , as in pic16 lc 74. these devices have eprom type memory and operate over an extended voltage range. 2.1 uv erasable devices the uv erasable version, offered in windowed cerdip packages, is optimal for prototype development and pilot programs. this version can be erased and reprogrammed to any of the oscillator modes. microchip's picstart ? plus and pro mate ? ii programmers both support programming of the pic16c63a/65b/73b/74b. 2.2 one-time-programmable (otp) devices the availability of otp devices is especially useful for customers who need the flexibility for frequent code updates and small volume applications. the otp devices, packaged in plastic packages, per- mit the user to program them once. in addition to the program memory, the configuration bits must also be programmed. 2.3 quick-turnaround-production (qtp) devices microchip offers a qtp programming service for fac- tory production orders. this service is made available for users who choose not to program a medium to high quantity of units and whose code patterns have stabi- lized. the devices are identical to the otp devices but with all eprom locations and configuration options already programmed by the factory. certain code and prototype verification procedures apply before produc- tion shipments are available. please contact your local microchip technology sales office for more details. 2.4 serialized quick-turnaround production (sqtp sm ) devices microchip offers a unique programming service where a few user-defined locations in each device are pro- grammed with different serial numbers. the serial num- bers may be random, pseudo-random or sequential. serial programming allows each device to have a unique number, which can serve as an entry code, password or id number.
pic16c63a/65b/73b/74b ds30605d-page 8 ? 1998-2013 microchip technology inc. notes:
? 1998-2013 microchip technology inc. ds30605d-page 9 pic16c63a/65b/73b/74b 3.0 architectural overview the high performance of the pic16cxx family can be attributed to a number of architectural features com- monly found in risc microprocessors. to begin with, the pic16cxx uses a harvard architecture, in which program and data are accessed from separate memo- ries using separate buses. this improves bandwidth over traditional von neumann architecture, in which program and data are fetched from the same memory using the same bus. separating program and data buses further allows instructions to be sized differently than the 8-bit wide data word. instruction opcodes are 14-bits wide, making it possible to have all single word instructions. a 14-bit wide program memory access bus fetches a 14-bit instruction in a single cycle. a two-stage pipeline overlaps fetch and execution of instructions (example 3-1). consequently, most instructions execute in a single cycle (200 ns @ 20 mhz) except for program branches. all devices covered by this data sheet contain 4k x 14-bit program memory and 192 x 8-bit data memory. the pic16cxx can directly, or indirectly, address its register files or data memory. all special function reg- isters, including the program counter, are mapped in the data memory. the pic16cxx has an orthogonal (symmetrical) instruction set that makes it possible to carry out any operation on any register using any addressing mode. this symmetrical nature and lack of ?special optimal situations? make programming with the pic16cxx simple yet efficient. in addition, the learning curve is reduced significantly. pic16cxx devices contain an 8-bit alu and working register. the alu is a general purpose arithmetic unit. it performs arithmetic and boolean functions between the data in the working register and any register file. the alu is 8-bits wide and capable of addition, sub- traction, shift and logical operations. unless otherwise mentioned, arithmetic operations are two's comple- ment in nature. in two-operand instructions, typically one operand is the working register (w register). the other operand is a file register or an immediate con- stant. in single operand instructions, the operand is either the w register or a file register. the w register is an 8-bit working register used for alu operations. it is not an addressable register. depending on the instruction executed, the alu may affect the values of the carry (c), digit carry (dc), and zero (z) bits in the status register. the c and dc bits operate as a borrow bit and a digit borrow out bit, respectively, in subtraction. see the sublw and subwf instructions for examples.
pic16c63a/65b/73b/74b ds30605d-page 10 ? 1998-2013 microchip technology inc. figure 3-1: pic16c63a/65 b/73b/74b block diagram eprom program memory 13 data bus 8 14 program bus instruction reg program counter 8 level stack (13-bit) ram file registers direct addr 7 ram addr (1) 9 addr mux indirect addr fsr reg status reg mux alu w reg power-up timer oscillator start-up timer power-on reset watchdog timer instruction decode & control timing generation osc1/clkin osc2/clkout mclr v dd , v ss porta portb portc portd (3) porte (3) ra4/t0cki ra5/ss /an4 (2) rb0/int rb7:rb1 rc0/t1oso/t1cki rc1/t1osi/ccp2 rc2/ccp1 rc3/sck/scl rc4/sdi/sda rc5/sdo rc6/tx/ck rc7/rx/dt rd6/psp6 re0/rd /an5 (2,3) re1/wr /an6 (2,3) re2/cs /an7 (2,3) 8 8 brown-out reset note 1: higher order bits are from the status register. 2: a/d is not available on the pic16c63a/65b. 3: psp and ports d and e are not available on pic16c63a/73b. usart ccp1 ccp2 synchronous a/d (2) timer0 timer1 timer2 serial port ra3/an3/v ref (2) ra2/an2 (2) ra1/an1 (2) ra0/an0 (2) parallel slave port 8 3 (3) rd1/psp1 rd2/psp2 rd3/psp3 rd4/psp4 rd5/psp5 rd0/psp0 rd7/psp7
? 1998-2013 microchip technology inc. ds30605d-page 11 pic16c63a/65b/73b/74b table 3-1: pic16c63a/73b pinout description pin name dip pin# soic pin# i/o/p type buffer type description osc1/clkin 9 9 i st/cmos (3) oscillator crystal input/external clock source input. osc2/clkout 10 10 o ? oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. in rc mode, the osc2 pin outputs clkout which has 1/4 the frequency of osc1, and denotes the instruction cycle rate. mclr /v pp 1 1 i/p st master clear (reset) input or programming voltage input. this pin is an active low reset to the device. porta is a bi-directional i/o port. ra0/an0 (4) 2 2 i/o ttl ra0 can also be analog input 0 (4) . ra1/an1 (4) 3 3 i/o ttl ra1 can also be analog input 1 (4) . ra2/an2 (4) 4 4 i/o ttl ra2 can also be analog input 2 (4) . ra3/an3/v ref (4) 5 5 i/o ttl ra3 can also be analog input 3 or analog reference voltage (4) . ra4/t0cki 6 6 i/o st ra4 can also be the clock input to the timer0 module. output is open drain type. ra5/ss/an4 (4) 7 7 i/o ttl ra5 can also be analog input 4 (4) or the slave select for the synchronous serial port. portb is a bi-directional i/o port. portb can be software programmed for internal weak pull-up on all inputs. rb0/int 21 21 i/o ttl/st (1) rb0 can also be the external interrupt pin. rb1 22 22 i/o ttl rb2 23 23 i/o ttl rb3 24 24 i/o ttl rb4 25 25 i/o ttl interrupt-on-change pin. rb5 26 26 i/o ttl interrupt-on-change pin. rb6 27 27 i/o ttl/st (2) interrupt-on-change pin. serial programming clock. rb7 28 28 i/o ttl/st (2) interrupt-on-change pin. serial programming data. portc is a bi-directional i/o port. rc0/t1oso/t1cki 11 11 i/o st rc0 can also be the timer1 oscillator output or timer1 clock input. rc1/t1osi/ccp2 12 12 i/o st rc1 can also be the timer1 oscillator input or capture2 input/compare2 output/pwm2 output. rc2/ccp1 13 13 i/o st rc2 can also be the capture1 input/compare1 output/pwm1 output. rc3/sck/scl 14 14 i/o st rc3 can also be the synchronous serial clock input/output for both spi and i 2 c modes. rc4/sdi/sda 15 15 i/o st rc4 can also be the spi data in (spi mode) or data i/o (i 2 c mode). rc5/sdo 16 16 i/o st rc5 can also be the spi data out (spi mode). rc6/tx/ck 17 17 i/o st rc6 can also be the usart asynchronous transmit or synchronous clock. rc7/rx/dt 18 18 i/o st rc7 can also be the usart asynchronous receive or synchronous data. v ss 8, 19 8, 19 p ? ground reference for logic and i/o pins. v dd 20 20 p ? positive supply for logic and i/o pins. legend: i = input o = output i/o = input/output p = power ? = not used ttl = ttl input st = schmitt trigger input note 1: this buffer is a schmitt trigger input w hen configured as the external interrupt. 2: this buffer is a schmitt trigger input when used in serial programming mode. 3: this buffer is a schmitt trigger input when confi gured in rc oscillator mode and a cmos input otherwise. 4: a/d module is not available in the pic16c63a.
pic16c63a/65b/73b/74b ds30605d-page 12 ? 1998-2013 microchip technology inc. table 3-2: pic16c65b/74 b pinout description pin name dip pin# plcc pin# tqfp mqfp pin# i/o/p type buffer type description osc1/clkin 13 14 30 i st/cmos (4) oscillator crystal input/external clock source input. osc2/clkout 14 15 31 o ? oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. in rc mode, osc2 pin outputs clkout which has 1/4 the frequency of osc1, and denotes the instruction cycle rate. mclr /v pp 1 2 18 i/p st master clear (reset) input or programming voltage input. this pin is an active low reset to the device. porta is a bi-directional i/o port. ra0/an0 (5) 2 3 19 i/o ttl ra0 can also be analog input 0 (5) . ra1/an1 (5) 3 4 20 i/o ttl ra1 can also be analog input 1 (5) . ra2/an2 (5) 4 5 21 i/o ttl ra2 can also be analog input 2 (5) . ra3/an3/v ref (5) 5 6 22 i/o ttl ra3 can also be analog input 3 or analog reference voltage (5) . ra4/t0cki 6 7 23 i/o st ra4 can also be the clock input to the timer0 timer/ counter. output is open drain type. ra5/ss /an4 (5) 7 8 24 i/o ttl ra5 can also be analog input 4 (5) or the slave select for the synchronous serial port. portb is a bi-directional i/o port. portb can be software programmed for internal weak pull-up on all inputs. rb0/int 33 36 8 i/o ttl/st (1) rb0 can also be the external interrupt pin. rb1 34 37 9 i/o ttl rb2 35 38 10 i/o ttl rb3 36 39 11 i/o ttl rb4 37 41 14 i/o ttl interrupt-on-change pin. rb5 38 42 15 i/o ttl interrupt-on-change pin. rb6 39 43 16 i/o ttl/st (2) interrupt-on-change pin. serial programming clock. rb7 40 44 17 i/o ttl/st (2) interrupt-on-change pin. serial programming data. legend: i = input o = output i/o = input/output p = power ? = not used ttl = ttl input st = schmitt trigger input note 1: this buffer is a schmitt trigger input w hen configured as the external interrupt. 2: this buffer is a schmitt trigger input when used in serial programming mode. 3: this buffer is a schmitt trigger input when configured as general purpose i/o and a ttl input when used in the parallel slave port mode (for interfacing to a microprocessor bus). 4: this buffer is a schmitt trigger input when confi gured in rc oscillator mode and a cmos input otherwise. 5: a/d is not available on the pic16c65b.
? 1998-2013 microchip technology inc. ds30605d-page 13 pic16c63a/65b/73b/74b portc is a bi-directional i/o port. rc0/t1oso/t1cki 15 16 32 i/o st rc0 can also be the timer1 oscillator output or a timer1 clock input. rc1/t1osi/ccp2 16 18 35 i/o st rc1 can also be the timer1 oscillator input or capture2 input/compare2 output/pwm2 output. rc2/ccp1 17 19 36 i/o st rc2 can also be the capture1 input/compare1 output/ pwm1 output. rc3/sck/scl 18 20 37 i/o st rc3 can also be the synchronous serial clock input/ output for both spi and i 2 c modes. rc4/sdi/sda 23 25 42 i/o st rc4 can also be the spi data in (spi mode) or data i/o (i 2 c mode). rc5/sdo 24 26 43 i/o st rc5 can also be the spi data out (spi mode). rc6/tx/ck 25 27 44 i/o st rc6 can also be the usart asynchronous transmit or synchronous clock. rc7/rx/dt 26 29 1 i/o st rc7 can also be the usart asynchronous receive or synchronous data. portd is a bi-directional i/ o port or parallel slave port when interfacing to a microprocessor bus. rd0/psp0 19 21 38 i/o st/ttl (3) rd1/psp1 20 22 39 i/o st/ttl (3) rd2/psp2 21 23 40 i/o st/ttl (3) rd3/psp3 22 24 41 i/o st/ttl (3) rd4/psp4 27 30 2 i/o st/ttl (3) rd5/psp5 28 31 3 i/o st/ttl (3) rd6/psp6 29 32 4 i/o st/ttl (3) rd7/psp7 30 33 5 i/o st/ttl (3) porte is a bi-directional i/o port. re0/rd /an5 (5) 8925i/ost/ttl (3) re0 can also be read control for the parallel slave port, or analog input 5 (5) . re1/wr /an6 (5) 91026i/ost/ttl (3) re1 can also be write control for the parallel slave port, or analog input 6 (5) . re2/cs /an7 (5) 10 11 27 i/o st/ttl (3) re2 can also be select control for the parallel slave port, or analog input 7 (5) . v ss 12,31 13,34 6,29 p ? ground reference for logic and i/o pins. v dd 11,32 12,35 7,28 p ? positive supply for logic and i/o pins. nc ? 1,17,28, 40 12,13, 33,34 ? these pins are not internally connected. these pins should be left unconnected. table 3-2: pic16c65b/74b pinout description (continued) pin name dip pin# plcc pin# tqfp mqfp pin# i/o/p type buffer type description legend: i = input o = output i/o = input/output p = power ? = not used ttl = ttl input st = schmitt trigger input note 1: this buffer is a schmitt trigger input w hen configured as the external interrupt. 2: this buffer is a schmitt trigger input when used in serial programming mode. 3: this buffer is a schmitt trigger input when configured as general purpose i/o and a ttl input when used in the parallel slave port mode (for interfacing to a microprocessor bus). 4: this buffer is a schmitt trigger input when confi gured in rc oscillator mode and a cmos input otherwise. 5: a/d is not available on the pic16c65b.
pic16c63a/65b/73b/74b ds30605d-page 14 ? 1998-2013 microchip technology inc. 3.1 clocking scheme/instruction cycle the clock input (from osc1) is internally divided by four to generate four non-overlapping quadrature clocks, namely q1, q2, q3 and q4. internally, the pro- gram counter (pc) is incremented every q1, the instruction is fetched from the program memory and latched into the instruction register in q4. the instruc- tion is decoded and executed during the following q1 through q4. the clocks and instruction execution flow is shown in figure 3-2. 3.2 instruction flow/pipelining an ?instruction cycle? consists of four q cycles (q1, q2, q3 and q4). the instruction fetch and execute are pipelined such that fetch takes one instruction cycle, while decode and execute takes another instruction cycle. however, due to the pipelining, each instruction effectively executes in one cycle. if an instruction causes the program counter to change (e.g., goto ), then two cycles are required to complete the instruction (example 3-1). a fetch cycle begins with the program counter (pc) incrementing in q1. in the execution cycle, the fetched instruction is latched into the ?instruction register" (ir) in cycle q1. this instruction is then decoded and executed during the q2, q3 and q4 cycles. data memory is read during q2 (operand read) and written during q4 (destination write). figure 3-2: clock /instruction cycle example 3-1: instruction pipeline flow q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 q1 q2 q3 q4 pc osc2/clkout (rc mode) pc pc+1 pc+2 fetch inst (pc) execute inst (pc-1) fetch inst (pc+1) execute inst (pc) fetch inst (pc+2) execute inst (pc+1) internal phase clock note: all instructions are single cycle, except for any program br anches. these take two cycles, since the fetch instruction is ?flushed? from the pipeline, while the new instruction is being fetched and then executed. t cy 0t cy 1t cy 2t cy 3t cy 4t cy 5 1. movlw 55h fetch 1 execute 1 2. movwf portb fetch 2 execute 2 3. call sub_1 fetch 3 execute 3 4. bsf porta, bit3 (forced nop) fetch 4 flush 5. instruction @ address sub_1 fetch sub_1 execute sub_1
? 1998-2013 microchip technology inc. ds30605d-page 15 pic16c63a/65b/73b/74b 4.0 memory organization 4.1 program memory organization the pic16c63a/65b/73b/74b has a 13-bit program counter capable of addressing an 8k x 14 program memory space. all devices covered by this data sheet have 4k x 14 bits of program memory. the address range is 0000h - 0fffh for all devices. accessing a location above 0fffh will cause a wrap- around. the reset vector is at 0000h and the interrupt vector is at 0004h. figure 4-1: pic16c63a/65b/73b/74b program memory map and stack 4.2 data memory organization the data memory is partitioned into multiple banks which contain the general purpose registers (gpr) and the special function registers (sfr). bits rp1 and rp0 are the bank select bits. rp1:rp0 (status<6:5>) = 00 ? bank0 = 01 ? bank1 = 10 ? bank2 = 11 ? bank3 each bank extends up to 7fh (128 bytes). the lower locations of each bank are reserved for the sfrs. above the sfrs are gprs, implemented as static ram. all implemented banks contain sfrs. frequently used sfrs from one bank may be mirrored in another bank for code reduction and quicker access. 4.2.1 general purpose register file the register file can be accessed either directly, or indi- rectly, through the file select register (fsr) (section 4.5). pc<12:0> 13 0000h 0004h 0005h 07ffh 0800h 0fffh 1000h 1fffh stack level 1 stack level 8 reset vector interrupt vector on-chip program on-chip program memory (page 1) memory (page 0) call,return retfie,retlw user memory space note: maintain the irp and rp1 bits clear in these devices.
pic16c63a/65b/73b/74b ds30605d-page 16 ? 1998-2013 microchip technology inc. figure 4-2: register file map 4.2.2 special function registers the special function registers are registers used by the cpu and peripheral modules for controlling the desired operation of the device. these registers are implemented as static ram. the special function registers can be classified into two sets (core and peripheral). those registers associ- ated with the ?core? functions are described in this sec- tion, and those related to the operation of the peripheral features are described in the section of that peripheral feature. indf (1) tmr0 pcl status fsr porta portb portc portd (2) porte (2) pclath intcon pir1 pir2 tmr1l tmr1h t1con tmr2 t2con sspbuf sspcon ccpr1l ccpr1h ccp1con rcsta txreg rcreg ccpr2l ccpr2h ccp2con adres (3) adcon0 (3) indf (1) option_reg pcl status fsr trisa trisb trisc trisd (2) trise (2) pclath intcon pie1 pie2 pcon pr2 sspadd sspstat txsta spbrg adcon1 (3) 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8ah 8bh 8ch 8dh 8eh 8fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9ah 9bh 9ch 9dh 9eh 9fh 20h a0h general purpose register general purpose register 7fh ffh bank 0 bank 1 file address file address u nimplemented data memory locations, read as ?0?. note 1: not a physical register. 2: these registers are not implemented on the pic16c63a/73b, read as '0'. 3: these registers are not implemented on the pic16c63a/65b, read as '0'.
? 1998-2013 microchip technology inc. ds30605d-page 17 pic16c63a/65b/73b/74b table 4-1: special function register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets (3) bank 0 00h indf (4) addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 0000 0000 01h tmr0 timer0 module?s register xxxx xxxx uuuu uuuu 02h pcl (4) program counter's (pc) least significant byte 0000 0000 0000 0000 03h status (4) irp (2) rp1 (2) rp0 to pd zdcc 0001 1xxx 000q quuu 04h fsr (4) indirect data memory address pointer xxxx xxxx uuuu uuuu 05h porta ? ? porta data latch when written: porta pins when read --0x 0000 --0u 0000 06h portb portb data latch when written: portb pins when read xxxx xxxx uuuu uuuu 07h portc portc data latch when written: portc pins when read xxxx xxxx uuuu uuuu 08h portd (5) portd data latch when written: portd pins when read xxxx xxxx uuuu uuuu 09h porte (5) ? ? ? ? ?re2re1re0 ---- -xxx ---- -uuu 0ah pclath (1,4) ? ? ? write buffer for the upper 5 bits of the program counter ---0 0000 ---0 0000 0bh intcon (4) gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (5) adif (6) rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 0dh pir2 ? ? ? ? ? ? ?ccp2if ---- ---0 ---- ---0 0eh tmr1l holding register for the least significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 0fh tmr1h holding register for the most significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 10h t1con ? ? t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on --00 0000 --uu uuuu 11h tmr2 timer2 module?s register 0000 0000 0000 0000 12h t2con ? toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 13h sspbuf synchronous serial port receive buffer/transmit register xxxx xxxx uuuu uuuu 14h sspcon wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 0000 0000 15h ccpr1l capture/compare/pwm register1 (lsb) xxxx xxxx uuuu uuuu 16h ccpr1h capture/compare/pwm register1 (msb) xxxx xxxx uuuu uuuu 17h ccp1con ? ? ccp1x ccp1y ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 --00 0000 18h rcsta spen rx9 sren cren ? ferr oerr rx9d 0000 -00x 0000 -00x 19h txreg usart transmit data register 0000 0000 0000 0000 1ah rcreg usart receive data register 0000 0000 0000 0000 1bh ccpr2l capture/compare/pwm register2 (lsb) xxxx xxxx uuuu uuuu 1ch ccpr2h capture/compare/pwm register2 (msb) xxxx xxxx uuuu uuuu 1dh ccp2con ? ? ccp2x ccp2y ccp2m3 ccp2m2 ccp2m1 ccp2m0 --00 0000 --00 0000 1eh adres (6) a/d result register xxxx xxxx uuuu uuuu 1fh adcon0 (6) adcs1 adcs0 chs2 chs1 chs0 go/done ?adon 0000 00-0 0000 00-0 legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0'. shaded locations are unimplemented, read as ?0?. note 1: the upper byte of the program counter is not directly accessible. pclath is a holding register for the pc<12:8>. 2: the irp and rp1 bits are reserved; always maintain these bits clear. 3: other (non power-up) resets in clude external reset through mclr and watchdog timer reset. 4: these registers can be addressed from either bank. 5: portd, porte and the parallel slave port are not implemented on the pic16c63a/73b; always maintain these bits and registers clear. 6: the a/d is not implemented on the pic16c63a/65b; always maintain these bits and registers clear.
pic16c63a/65b/73b/74b ds30605d-page 18 ? 1998-2013 microchip technology inc. bank 1 80h indf (4) addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 0000 0000 81h option_reg rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 82h pcl (4) program counter's (pc) least significant byte 0000 0000 0000 0000 83h status (4) irp (2) rp1 (2) rp0 to pd zdcc 0001 1xxx 000q quuu 84h fsr (4) indirect data memory address pointer xxxx xxxx uuuu uuuu 85h trisa ? ? porta data direction register --11 1111 --11 1111 86h trisb portb data direction register 1111 1111 1111 1111 87h trisc portc data direction register 1111 1111 1111 1111 88h trisd (5) portd data direction register 1111 1111 1111 1111 89h trise (5) ibf obf ibov pspmode ? porte data direction bits 0000 -111 0000 -111 8ah pclath (1,4) ? ? ? write buffer for the upper 5 bits of the program counter ---0 0000 ---0 0000 8bh intcon (4) gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 8ch pie1 pspie (5) adie (6) rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 8dh pie2 ? ? ? ? ? ? ? ccp2ie ---- ---0 ---- ---0 8eh pcon ? ? ? ? ? ?por bor ---- --qq ---- --uu 8fh ? unimplemented ? ? 90h ? unimplemented ? ? 91h ? unimplemented ? ? 92h pr2 timer2 period register 1111 1111 1111 1111 93h sspadd synchronous serial port (i 2 c mode) address register 0000 0000 0000 0000 94h sspstat ? ?d/a psr/w ua bf --00 0000 --00 0000 95h ? unimplemented ? ? 96h ? unimplemented ? ? 97h ? unimplemented ? ? 98h txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 9ah ? unimplemented ? ? 9bh ? unimplemented ? ? 9ch ? unimplemented ? ? 9dh ? unimplemented ? ? 9eh ? unimplemented ? ? 9fh adcon1 (6) ? ? ? ? ? pcfg2 pcfg1 pcfg0 ---- -000 ---- -000 table 4-1: special function register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets (3) legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0'. shaded locations are unimplemented, read as ?0?. note 1: the upper byte of the program counter is not directly accessible. pclath is a holding register for the pc<12:8>. 2: the irp and rp1 bits are reserved; always maintain these bits clear. 3: other (non power-up) resets in clude external reset through mclr and watchdog timer reset. 4: these registers can be addressed from either bank. 5: portd, porte and the parallel slave port are not implemented on the pic16c63a/73b; always maintain these bits and registers clear. 6: the a/d is not implemented on the pic16c63a/65b; always maintain these bits and registers clear.
? 1998-2013 microchip technology inc. ds30605d-page 19 pic16c63a/65b/73b/74b 4.2.2.1 status register the status register, shown in register 4-1, contains the arithmetic status of the alu, the reset status and the bank select bits for data memory. the status register can be the destination for any instruction, as with any other register. if the status reg- ister is the destination for an instruction that affects the z, dc or c bits, then the write to these three bits is disabled. these bits are set or cleared according to the device logic. furthermore, the to and pd bits are not writable. therefore, the result of an instruction with the status register as destination may be different than intended. for example, clrf status will clear the upper three bits and set the z bit. this leaves the status register as 000u u1uu (where u = unchanged). it is recommended that only bcf, bsf, swapf and movwf instructions be used to alter the status regis- ter. these instructions do not affect the z, c or dc bits in the status register. for other instructions which do not affect status bits, see the "instruction set sum- mary." register 4-1: status register (address 03h, 83h) note 1: these devices do not use bits irp and rp1 (status<7:6>), maintain these bits clear to ensure upward compatibility with future products. 2: the c and dc bits operate as borrow and digit borrow bits, respectively, in subtrac- tion. see the sublw and subwf instruc- tions for examples. r/w-0 r/w-0 r/w-0 r-1 r-1 r/w-x r/w-x r/w-x irp (1) rp1 (1) rp0 to pd z dc c (2) bit 7 bit 0 bit 7 irp (1) : register bank select bit (used for indirect addressing) 1 = bank 2, 3 (100h - 1ffh) 0 = bank 0, 1 (00h - ffh) bit 6-5 rp1 (1) :rp0: register bank select bits (used for direct addressing) 11 = bank 3 (180h - 1ffh) 10 = bank 2 (100h - 17fh) 01 = bank 1 (80h - ffh) 00 = bank 0 (00h - 7fh) each bank is 128 bytes bit 4 to : time-out bit 1 = after power-up, clrwdt instruction, or sleep instruction 0 = a wdt time-out occurred bit 3 pd : power-down bit 1 = after power-up or by the clrwdt instruction 0 = by execution of the sleep instruction bit 2 z: zero bit 1 = the result of an arithmetic or logic operation is zero 0 = the result of an arithmetic or logic operation is not zero bit 1 dc: digit carry/borrow bit ( addwf,addlw,sublw,subwf instructions) (for borrow the polarity is reversed) 1 = a carry-out from the 4th low order bit of the result occurred 0 = no carry-out from the 4th low order bit of the result bit 0 c (2) : carry/borrow bit ( addwf,addlw,sublw,subwf instructions) 1 = a carry-out from the most significant bit of the result occurred 0 = no carry-out from the most significant bit of the result occurred note 1: maintain the irp and rp1 bits clear. 2: for borrow and digit borrow , the polarity is reversed. a subtraction is executed by adding the two?s complement of the second operand. for rotate ( rrf,rlf ) instruc- tions, this bit is loaded with either the high or low order bit of the source register. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic16c63a/65b/73b/74b ds30605d-page 20 ? 1998-2013 microchip technology inc. 4.2.2.2 option register the option_reg register is a readable and writable register, which contains various control bits to configure the tmr0/wdt prescaler, the external int interrupt, tmr0 and the weak pull-ups on portb. register 4-2: option_reg register (address 81h) note: to achieve a 1:1 prescaler assignment for the tmr0 register, assign the prescaler to the watchdog timer. r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 rbpu intedg t0cs t0se psa ps2 ps1 ps0 bit 7 bit 0 bit 7 rbpu : portb pull-up enable bit 1 = portb pull-ups are disabled 0 = portb pull-ups are enabled by individual port latch values bit 6 intedg: interrupt edge select bit 1 = interrupt on rising edge of rb0/int pin 0 = interrupt on falling edge of rb0/int pin bit 5 t0cs: tmr0 clock source select bit 1 = transition on ra4/t0cki pin 0 = internal instruction cycle clock (clkout) bit 4 t0se: tmr0 source edge select bit 1 = increment on high-to-low transition on ra4/t0cki pin 0 = increment on low-to-high transition on ra4/t0cki pin bit 3 psa: prescaler assignment bit 1 = prescaler is assigned to the wdt 0 = prescaler is assigned to the timer0 module bit 2-0 ps2:ps0: prescaler rate select bits legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 bit value tmr0 rate wdt rate
? 1998-2013 microchip technology inc. ds30605d-page 21 pic16c63a/65b/73b/74b 4.2.2.3 intcon register the intcon register is a readable and writable regis- ter, which contains various enable and flag bits for the tmr0 register overflow, rb port change and external rb0/int pin interrupts. register 4-3: intcon register (address 0bh, 8bh) note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit, or the global enable bit, gie (intcon<7>). user soft- ware should ensure the appropriate inter- rupt flag bits are clear prior to enabling an interrupt . r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-x gie peie t0ie inte rbie t0if intf rbif bit 7 bit 0 bit 7 gie: global interrupt enable bit 1 = enables all unmasked interrupts 0 = disables all interrupts bit 6 peie : peripheral interrupt enable bit 1 = enables all unmasked peripheral interrupts 0 = disables all peripheral interrupts bit 5 t0ie : tmr0 overflow interrupt enable bit 1 = enables the tmr0 interrupt 0 = disables the tmr0 interrupt bit 4 inte : rb0/int external interrupt enable bit 1 = enables the rb0/int external interrupt 0 = disables the rb0/int external interrupt bit 3 rbie: rb port change interrupt enable bit 1 = enables the rb port change interrupt 0 = disables the rb port change interrupt bit 2 t0if : tmr0 overflow interrupt flag bit 1 = tmr0 register has overflowed (must be cleared in software) 0 = tmr0 register did not overflow bit 1 intf : rb0/int external interrupt flag bit 1 = the rb0/int external interrupt occurred (must be cleared in software) 0 = the rb0/int external interrupt did not occur bit 0 rbif : rb port change interrupt flag bit 1 = at least one of the rb7:rb4 pins changed state (1) 0 = none of the rb7:rb4 pins have changed state note 1: a mismatch condition will exist until portb is read. after reading portb, the rbif flag bit can be cleared. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic16c63a/65b/73b/74b ds30605d-page 22 ? 1998-2013 microchip technology inc. 4.2.2.4 pie1 register this register contains the individual enable bits for the peripheral interrupts. register 4-4: pie1 register (address 8ch) note: bit peie (intcon<6>) must be set to enable any peripheral interrupt. r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pspie (1) adie (2) rcie txie sspie ccp1ie tmr2ie tmr1ie bit 7 bit 0 bit 7 pspie (1) : parallel slave port read/write interrupt enable bit 1 = enables the psp read/write interrupt 0 = disables the psp read/write interrupt bit 6 adie (2) : a/d converter interrupt enable bit 1 = enables the a/d interrupt 0 = disables the a/d interrupt bit 5 rcie: usart receive interrupt enable bit 1 = enables the usart receive interrupt 0 = disables the usart receive interrupt bit 4 txie: usart transmit interrupt enable bit 1 = enables the usart transmit interrupt 0 = disables the usart transmit interrupt bit 3 sspie : synchronous serial port interrupt enable bit 1 = enables the ssp interrupt 0 = disables the ssp interrupt bit 2 ccp1ie: ccp1 interrupt enable bit 1 = enables the ccp1 interrupt 0 = disables the ccp1 interrupt bit 1 tmr2ie: tmr2 to pr2 match interrupt enable bit 1 = enables the tmr2 to pr2 match interrupt 0 = disables the tmr2 to pr2 match interrupt bit 0 tmr1ie: tmr1 overflow interrupt enable bit 1 = enables the tmr1 overflow interrupt 0 = disables the tmr1 overflow interrupt note 1: pic16c63a/73b devices do not have a parallel slave port implemented; always maintain this bit clear. 2: pic16c63a/65b devices do not have an a/d implemented; always maintain this bit clear. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 1998-2013 microchip technology inc. ds30605d-page 23 pic16c63a/65b/73b/74b 4.2.2.5 pir1 register this register contains the individual flag bits for the peripheral interrupts. register 4-5: pir1 register (address 0ch) note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit, or the global enable bit, gie (intcon<7>). user soft- ware should ensure the appropriate inter- rupt flag bits are clear prior to enabling an interrupt . r/w-0 r/w-0 r-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 pspif (1) adif (2) rcif txif sspif ccp1if tmr2if tmr1if bit 7 bit 0 bit 7 pspif (1) : parallel slave port read/write interrupt flag bit 1 = a read or a write operation has taken place (must be cleared in software) 0 = no read or write has occurred bit 6 adif (2) : a/d converter interrupt flag bit 1 = an a/d conversion completed (must be cleared in software) 0 = the a/d conversion is not complete bit 5 rcif : usart receive interrupt flag bit 1 = the usart receive buffer is full (clear by reading rcreg) 0 = the usart receive buffer is empty bit 4 txif : usart transmit interrupt flag bit 1 = the usart transmit buffer is empty (clear by writing to txreg) 0 = the usart transmit buffer is full bit 3 sspif : synchronous serial port interrupt flag bit 1 = the transmission/reception is complete (must be cleared in software) 0 = waiting to transmit/receive bit 2 ccp1if : ccp1 interrupt flag bit capture mode: 1 = a tmr1 register capture occurred (must be cleared in software) 0 = no tmr1 register capture occurred compare mode: 1 = a tmr1 register compare match occurred (must be cleared in software) 0 = no tmr1 register compare match occurred pwm mode: unused in this mode bit 1 tmr2if : tmr2 to pr2 match interrupt flag bit 1 = tmr2 to pr2 match occurred (must be cleared in software) 0 = no tmr2 to pr2 match occurred bit 0 tmr1if : tmr1 overflow interrupt flag bit 1 = tmr1 register overflowed (must be cleared in software) 0 = tmr1 register did not overflow note 1: pic16c63a/73b devices do not have a parallel slave port implemented. this bit loca- tion is reserved on these devices. 2: pic16c63a/65b devices do not have an a/d implemented. this bit location is reserved on these devices. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic16c63a/65b/73b/74b ds30605d-page 24 ? 1998-2013 microchip technology inc. 4.2.2.6 pie2 register this register contains the individual enable bit for the ccp2 peripheral interrupt. register 4-6: pie2 register (address 8dh) 4.2.2.7 pir2 register this register contains the ccp2 interrupt flag bit. register 4-7: pir2 register (address 0dh) u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 ? ? ? ? ? ? ? ccp2ie bit 7 bit 0 bit 7-1 unimplemented: read as '0' bit 0 ccp2ie : ccp2 interrupt enable bit 1 = enables the ccp2 interrupt 0 = disables the ccp2 interrupt legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit, or the global enable bit, gie (intcon<7>). user soft- ware should ensure the appropriate inter- rupt flag bits are clear prior to enabling an interrupt . u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 ? ? ? ? ? ? ? ccp2if bit 7 bit 0 bit 7-1 unimplemented: read as '0' bit 0 ccp2if : ccp2 interrupt flag bit capture mode: 1 = a tmr1 register capture occurred (must be cleared in software) 0 = no tmr1 register capture occurred compare mode: 1 = a tmr1 register compare match occurred (must be cleared in software) 0 = no tmr1 register compare match occurred pwm mode: unused legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 1998-2013 microchip technology inc. ds30605d-page 25 pic16c63a/65b/73b/74b 4.2.2.8 pcon register the power control (pcon) register contains flag bits to allow differentiation between a power-on reset (por), a brown-out reset (bor), a watchdog reset (wdt) and an external mclr reset. register 4-8: pcon register (address 8eh) note: bor is unknown on por. it must be set by the user and checked on subsequent resets to see if bor is clear, indicating a brown-out has occurred. the bor status bit is a ?don't care? and is not predictable if the brown-out circuit is disabled (by clear- ing the boden bit in the configuration word). u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-q ? ? ? ? ? ?por bor bit 7 bit 0 bit 7-2 unimplemented: read as '0' bit 1 por : power-on reset status bit 1 = no power-on reset occurred 0 = a power-on reset occurred (must be set in software after a power-on reset occurs) bit 0 bor : brown-out reset status bit 1 = no brown-out reset occurred 0 = a brown-out reset occurred (must be set in software after a brown-out reset occurs) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic16c63a/65b/73b/74b ds30605d-page 26 ? 1998-2013 microchip technology inc. 4.3 pcl and pclath the program counter (pc) is 13-bits wide. the low byte comes from the pcl register, which is a readable and writable register. the upper bits (pc<12:8>) are not readable, but are indirectly writable through the pclath register. on any reset, the upper bits of the pc will be cleared. figure 4-3 shows the two situations for the loading of the pc. the upper example in the fig- ure shows how the pc is loaded on a write to pcl (pclath<4:0> ? pch). the lower example in the fig- ure shows how the pc is loaded during a call or goto instruction (pclath<4:3> ? pch). figure 4-3: loading of pc in different situations 4.3.1 computed goto a computed goto is accomplished by adding an offset to the program counter ( addwf pcl ). when doing a table read using a computed goto method, care should be exercised if the table location crosses a pcl memory boundary (each 256 byte block). refer to the application note ?implementing a table read" (an556). 4.3.2 stack the pic16cxx family has an 8-level deep x 13-bit wide hardware stack. the stack space is not part of either program or data space and the stack pointer is not readable or writable. the pc is pushed onto the stack when a call instruction is executed, or an interrupt causes a branch. the stack is poped in the event of a return,retlw or a retfie instruction execution. pclath is not affected by a push or pop operation. the stack operates as a circular buffer. this means that after the stack has been pushed eight times, the ninth push overwrites the value that was stored from the first push. the tenth push overwrites the second push (and so on). 4.4 program memory paging pic16cxx devices are capable of addressing a contin- uous 8k word block of program memory. the call and goto instructions provide only 11 bits of address to allow branching within any 2k program memory page. when executing a call or goto instruction, the upper 2 bits of the address are provided by pclath<4:3>. when doing a call or goto instruction, the user must ensure that the page select bits are programmed, so that the desired program memory page is addressed. if a return from a call instruction (or interrupt) is exe- cuted, the entire 13-bit pc is popped from the stack. therefore, manipulation of the pclath<4:3> bits are not required for the return instructions (which pops the address from the stack). example 4-1 shows the calling of a subroutine in page 1 of the program memory. this example assumes that pclath is saved and restored by the interrupt service routine (if interrupts are used). example 4-1: call of a subroutine in page 1 from page 0 org 0x500 bsf pclath,3 ;select page 1 (800h-fffh) call sub1_p1 ;call subroutine in : ;page 1 (800h-fffh) : org 0x900 ;page 1 (800h-fffh) sub1_p1 : ;called subroutine : ;page 1 (800h-fffh) : return ;return to call subroutine ;in page 0 (000h-7ffh) pc 12 8 7 0 5 pclath<4:0> pclath instruction with alu goto,call opcode <10:0> 8 pc 12 11 10 0 11 pclath<4:3> pch pcl 87 2 pclath pch pcl pcl as destination note 1: there are no status bits to indicate stack overflow or stack underflow conditions. 2: there are no instructions/mnemonics called push or pop. these are actions that occur from the execution of the call, return, retlw, and retfie instructions, or the vectoring to an inter- rupt address. note 1: the contents of pclath are unchanged after a return or retfie instruction is executed. the user must set up pclath for any subsequent call ?s or goto ?s 2: pclath<4> is not used in these pic ? devices. the use of pclath<4> as a general purpose read/write bit is not rec- ommended, since this may affect upward compatibility with future products.
? 1998-2013 microchip technology inc. ds30605d-page 27 pic16c63a/65b/73b/74b 4.5 indirect addressing, indf and fsr registers the indf register is not a physical register. addressing the indf register will cause indirect addressing. indirect addressing is possible by using the indf reg- ister. any instruction using the indf register actually accesses the register pointed to by the file select reg- ister, fsr. reading the indf register itself indirectly (fsr = '0') will read 00h. writing to the indf register indirectly results in a no-operation (although status bits may be affected). an effective 9-bit address is obtained by concatenating the 8-bit fsr register and the irp bit (status<7>), as shown in figure 4-4. a simple program to clear ram locations 20h-2fh using indirect addressing is shown in example 4-2. example 4-2: indirect addressing movlw 0x20 ;initialize pointer movwf fsr ;to ram next clrf indf ;clear indf register incf fsr,f ;inc pointer btfss fsr,4 ;all done? goto next ;no clear next continue : ;yes continue figure 4-4: direct/indirect addressing note: maintain the irp and rp1 bits clear. note 1: for register file map detail, see figure 4-2. 2: shaded portions are not implemented; maintain the irp and rp1 bits clear. data memory indirect addressing direct addressing bank select location select rp1:rp0 6 0 from opcode irp fsr register 7 0 bank select location select 00 01 10 11 bank 0 bank 1 bank 2 bank 3 not used ffh 80h 7fh 00h 17fh 100h 1ffh 180h 0 0
pic16c63a/65b/73b/74b ds30605d-page 28 ? 1998-2013 microchip technology inc. notes:
? 1998-2013 microchip technology inc. ds30605d-page 29 pic16c63a/65b/73b/74b 5.0 i/o ports some pins for these i/o ports are multiplexed with an alternate function for the peripheral features on the device. in general, when a peripheral is enabled, that pin may not be used as a general purpose i/o pin. 5.1 porta and trisa registers porta is a 6-bit latch. the ra4/t0cki pin is a schmitt trigger input and an open drain output. all other ra port pins have ttl input levels and full cmos output drivers. all pins have data direction bits (tris registers), which can config- ure these pins as output or input. setting a trisa register bit puts the corresponding out- put driver in a hi-impedance mode. clearing a bit in the trisa register puts the contents of the output latch on the selected pin(s). reading the porta register reads the status of the pins, whereas writing to it will write to the port latch. all write operations are read-modify-write operations. therefore, a write to a port implies that the port pins are read, the value is modified and then written to the port data latch. pin ra4 is multiplexed with the timer0 module clock input to become the ra4/t0cki pin. on the pic16c73b/74b, porta pins are multiplexed with analog inputs and analog v ref input. the opera- tion of each pin is selected by clearing/setting the con- trol bits in the adcon1 register (a/d control register1). the trisa register controls the direction of the ra pins, even when they are being used as analog inputs. the user must ensure the bits in the trisa register are maintained set when using them as analog inputs. example 5-1: initializing porta (pic16c73b/74b) bcf status, rp0 ; clrf porta ; initialize porta by ; clearing output ; data latches bsf status, rp0 ; select bank 1 movlw 0x06 ; configure all pins movwf adcon1 ; as digital inputs movlw 0xcf ; value used to ; initialize data ; direction movwf trisa ; set ra<3:0> as inputs ; ra<5:4> as outputs ; trisa<7:6> are always ; read as '0'. figure 5-1: block diagram of ra3:ra0 and ra5 pins figure 5-2: block diagram of ra4/t0cki pin note: on all resets, pins with analog functions are configured as analog and digital inputs. data bus q d q ck q d q ck qd en p n wr port wr tris data latch tris latch rd tris rd port v ss v dd i/o pin (1) note 1: i/o pins have protection diodes to v dd and v ss . analog input mode ttl input buffer to a/d converter data bus wr port wr tris rd port data latch tris latch rd tris schmitt trigger input buffer n v ss i/o pin tmr0 clock input q d q ck q d q ck en qd en (1) note 1: i/o pins have protection diodes to v dd and v ss .
pic16c63a/65b/73b/74b ds30605d-page 30 ? 1998-2013 microchip technology inc. table 5-1: porta functions table 5-2: summary of registers associated with porta name bit# buffer function ra0/an0 (1) bit0 ttl digital input/output or analog input. ra1/an1 (1) bit1 ttl digital input/output or analog input. ra2/an2 (1) bit2 ttl digital input/output or analog input. ra3/an3/v ref (1) bit3 ttl digital input/output or analog input or v ref. ra4/t0cki bit4 st digital input/output or external clock input for timer0. output is open drain type. ra5/ss /an4 (1) bit5 ttl input/output or slave select input for synchronous serial port or analog input. legend: ttl = ttl input, st = schmitt trigger input note 1: the a/d is not implemented on the pic16c63a/65b. pins will operate as digital i/o only. adcon1 is not implemented; maintain this register clear. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 05h porta ? ? ra5 ra4 ra3 ra2 ra1 ra0 --0x 0000 --0u 0000 85h trisa ? ? porta data direction register --11 1111 --11 1111 9fh adcon1 (1) ? ? ? ? ? pcfg2 pcfg1 pcfg0 ---- -000 ---- -000 legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. shaded cells are not used by porta. note 1: the a/d is not implemented on the pic16c63a/65b. pins will operate as digital i/o only. adcon1 is not implemented; maintain this register clear.
? 1998-2013 microchip technology inc. ds30605d-page 31 pic16c63a/65b/73b/74b 5.2 portb and trisb registers portb is an 8-bit wide, bi-directional port. the corre- sponding data direction register is trisb. setting a bit in the trisb register puts the corresponding output driver in a hi-impedance input mode. clearing a bit in the trisb register puts the contents of the output latch on the selected pin(s). each of the portb pins has a weak internal pull-up. a single control bit can turn on all the pull-ups. this is per- formed by clearing bit rbpu (option_reg<7>). the weak pull-up is automatically turned off when the port pin is configured as an output. the pull-ups are dis- abled on a power-on reset. figure 5-3: blo ck diagram of rb3:rb0 pins four of portb?s pins, rb7:rb4, have an interrupt-on-change feature. only pins configured as inputs can cause this interrupt to occur (i.e., any rb7:rb4 pin configured as an output is excluded from the interrupt-on-change comparison). the input pins (of rb7:rb4) are compared with the value latched on the last read of portb. the ?mismatch? outputs of rb7:rb4 are or?d together to generate the rb port change interrupt with flag bit rbif (intcon<0>). this interrupt can wake the device from sleep. the user, in the interrupt service routine, can clear the interrupt in the following manner: a) any read or write of portb. this will end the mismatch condition. b) clear flag bit rbif. a mismatch condition will continue to set flag bit rbif. reading portb will end the mismatch condition, and allow flag bit rbif to be cleared. this interrupt-on-mismatch feature, together with soft- ware configurable pull-ups on these four pins, allow easy interface to a keypad and make it possible for wake-up on key depression. refer to the embedded control handbook, ?implementing wake-up on key stroke? (an552). the interrupt-on-change feature is recommended for wake-up on key depression operation and operations where portb is only used for the interrupt-on-change feature. polling of portb is not recommended while using the interrupt-on-change feature. rb0/int is an external interrupt input pin and is config- ured using the intedg bit (option_reg<6>). rb0/int is discussed in detail in section 13.5.1. figure 5-4: block diagram of rb7:rb4 pins data latch rbpu (2) p v dd q d ck q d ck qd en data bus wr port wr tris rd tris rd port weak pull-up rd port rb0/int i/o pin (1) ttl input buffer schmitt trigger buffer tris latch note 1: i/o pins have diode protection to v dd and v ss . 2: to enable weak pull-ups, set the appropriate tris bit(s) and clear the rbpu bit (option_reg<7>). data latch from other rbpu (2) p v dd i/o pin (1) q d ck q d ck qd en qd en data bus wr port wr tris set rbif tris latch rd tris rd port rb7:rb4 pins weak pull-up rd port latch ttl input buffer st buffer rb7:rb6 in serial programming mode q3 q1 note 1: i/o pins have diode protection to v dd and v ss . 2: to enable weak pull-ups, set the appropriate tris bit(s) and clear the rbpu bit (option_reg<7>).
pic16c63a/65b/73b/74b ds30605d-page 32 ? 1998-2013 microchip technology inc. table 5-3: portb functions table 5-4: summary of registers associated with portb name bit# buffer function rb0/int bit0 ttl/st (1) input/output pin or external interrupt input. internal software programmable weak pull-up. rb1 bit1 ttl input/output pin. internal software programmable weak pull-up. rb2 bit2 ttl input/output pin. internal software programmable weak pull-up. rb3 bit3 ttl input/output pin. internal software programmable weak pull-up. rb4 bit4 ttl input/output pin (with interrupt-on- change). internal software programmable weak pull-up. rb5 bit5 ttl input/output pin (with interrupt-on- change). internal software programmable weak pull-up. rb6 bit6 ttl/st (2) input/output pin (with interrupt-on-change) . internal software programmable weak pull-up. serial programming clock. rb7 bit7 ttl/st (2) input/output pin (with interrupt-on-change) . internal software programmable weak pull-up. serial programming data. legend: ttl = ttl input, st = schmitt trigger input note 1: this buffer is a schmitt trigger input when configured as the external interrupt. 2: this buffer is a schmitt trigger input when used in serial programming mode. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 06h portb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 xxxx xxxx uuuu uuuu 86h trisb portb data direction register 1111 1111 1111 1111 81h option_reg rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 legend: x = unknown, u = unchanged. shaded cells are not used by portb.
? 1998-2013 microchip technology inc. ds30605d-page 33 pic16c63a/65b/73b/74b 5.3 portc and trisc registers portc is an 8-bit bi-directional port. each pin is indi- vidually configurable as an input or output through the trisc register. portc is multiplexed with several peripheral functions (table 5-5). portc pins have schmitt trigger input buffers. when enabling peripheral functions, care should be taken in defining tris bits for each portc pin. some peripherals override the tris bit to make a pin an out- put, while other peripherals override the tris bit to make a pin an input. since the tris bit override is in effect while the peripheral is enabled, read-modify-write instructions ( bsf, bcf, xorwf ) with trisc as des- tination should be avoided. the user should refer to the corresponding peripheral section for the correct tris bit settings. figure 5-5: port c block diagram table 5-5: portc functions table 5-6: summary of regist ers associated with portc port/peripheral select (2) data bus wr port wr tris rd data latch tris latch rd tris schmitt trigger q d q ck qd en peripheral data out 0 1 q d q ck p n v dd v ss port peripheral oe (3) peripheral input i/o pin (1) note 1: i/o pins have diode protection to v dd and v ss . 2: port/peripheral select signal selects between port data and peripheral output. 3: peripheral oe (output enable) is only activated if peripheral select is active. name bit# buffer type function rc0/t1oso/t1cki bit0 st input/output port pin or timer1 oscillator output/timer1 clock input. rc1/t1osi/ccp2 bit1 st input/output port pin or time r1 oscillator input or capture2 input/compare2 output/pwm2 output. rc2/ccp1 bit2 st input/output port pin or c apture1 input/compare1 output/pwm1 output. rc3/sck/scl bit3 st rc3 can also be the synchronous serial clock for both spi and i 2 c modes. rc4/sdi/sda bit4 st rc4 can also be the spi data in (spi mode) or data i/o (i 2 c mode). rc5/sdo bit5 st input/output port pin or synchronous serial port data output. rc6/tx/ck bit6 st input/output port pin or usart asynchronous transmit, or usart synchronous clock. rc7/rx/dt bit7 st input/output port pin or usart asynchronous receive, or usart synchronous data. legend: st = schmitt trigger input address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 07h portc rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 xxxx xxxx uuuu uuuu 87h trisc portc data direction register 1111 1111 1111 1111 legend: x = unknown, u = unchanged
pic16c63a/65b/73b/74b ds30605d-page 34 ? 1998-2013 microchip technology inc. 5.4 portd and trisd registers portd is an 8-bit port with schmitt trigger input buff- ers. each pin is individually configured as an input or output. portd can be configured as an 8-bit wide micropro- cessor port (parallel slave port) by setting control bit pspmode (trise<4>). in this mode, the input buffers are ttl. figure 5-6: port d block diagram table 5-7: portd functions table 5-8: summary of registers associated with portd note: the pic16c63a and pic16c73b do not provide portd. the portd and trisd registers are not implemented. data bus wr port wr tris rd port data latch tris latch rd tris schmitt trigger input buffer i/o pin (1) q d ck q d ck en qd en note 1: i/o pins have protection diodes to v dd and v ss . name bit# buffer type function rd0/psp0 bit0 st/ttl (1) input/output port pin or parallel slave port bit0 rd1/psp1 bit1 st/ttl (1) input/output port pin or parallel slave port bit1 rd2/psp2 bit2 st/ttl (1) input/output port pin or parallel slave port bit2 rd3/psp3 bit3 st/ttl (1) input/output port pin or parallel slave port bit3 rd4/psp4 bit4 st/ttl (1) input/output port pin or parallel slave port bit4 rd5/psp5 bit5 st/ttl (1) input/output port pin or parallel slave port bit5 rd6/psp6 bit6 st/ttl (1) input/output port pin or parallel slave port bit6 rd7/psp7 bit7 st/ttl (1) input/output port pin or parallel slave port bit7 legend: st = schmitt trigger input, ttl = ttl input note 1: input buffers are schmitt triggers when in i/o mode and ttl buffer when in parallel slave port mode. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 08h portd rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 xxxx xxxx uuuu uuuu 88h trisd portd data direction register 1111 1111 1111 1111 89h trise ibf obf ibov pspmode ? porte data direction bits 0000 -111 0000 -111 legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. s haded cells are not used by portd.
? 1998-2013 microchip technology inc. ds30605d-page 35 pic16c63a/65b/73b/74b 5.5 porte and trise register porte has three pins: re0/rd /an5, re1/wr /an6 and re2/cs /an7, which are individually configured as inputs or outputs. these pins have schmitt trigger input buffers. i/o porte becomes control inputs for the micropro- cessor port when bit pspmode (trise<4>) is set. in this mode, the user must make sure that the trise<2:0> bits are set (pins are configured as digital inputs) and that register adcon1 is configured for dig- ital i/o. in this mode, the input buffers are ttl. register 5-1 shows the trise register, which also con- trols the parallel slave port operation. porte pins may be multiplexed with analog inputs (pic16c74b only). the operation of these pins is selected by control bits in the adcon1 register. when selected as an analog input, these pins will read as '0's. trise controls the direction of the re pins, even when they are being used as analog inputs. the user must make sure to keep the pins configured as inputs when using them as analog inputs. figure 5-7: port e block diagram table 5-9: porte functions note 1: the pic16c63a and pic16c73b do not provide porte. the porte and trise registers are not implemented. 2: the pic16c63a/65b does not provide an a/d module. a/d functions are not imple- mented. note: on a power-on reset, these pins are con- figured as analog inputs and read as ?0?s. data bus wr port wr tris rd port data latch tris latch rd tris schmitt trigger input buffer q d ck q d ck en qd en i/o pin (1) note 1: i/o pins have protection diodes to v dd and v ss . name bit# buffer type function re0/rd /an5 bit0 st/ttl (1) input/output port pin or read control input in parallel slave port mode or analog input: rd 1 = idle 0 = read operation. contents of portd register is output to portd i/o pins (if chip selected). re1/wr /an6 bit1 st/ttl (1) input/output port pin or write control input in parallel slave port mode or analog input: wr 1 = idle 0 = write operation. value of portd i/o pins is latched into portd register (if chip selected). re2/cs /an7 bit2 st/ttl (1) input/output port pin or chip select control input in parallel slave port mode or analog input: cs 1 = device is not selected 0 = device is selected legend: st = schmitt trigger input, ttl = ttl input note 1: input buffers are schmitt triggers when in i/o mode and ttl buffers when in parallel slave port mode.
pic16c63a/65b/73b/74b ds30605d-page 36 ? 1998-2013 microchip technology inc. register 5-1: trise register (address 89h) table 5-10: summary of regist ers associated with porte r-0 r-0 r/w-0 r/w-0 u-0 r/w-1 r/w-1 r/w-1 ibf obf ibov pspmode ? trise2 trise1 trise0 bit 7 bit 0 bit 7 ibf: input buffer full status bit 1 = a word has been received and is waiting to be read by the cpu 0 = no word has been received bit 6 obf: output buffer full status bit 1 = the output buffer still holds a previously written word 0 = the output buffer has been read bit 5 ibov: input buffer overflow detect bit (in microprocessor mode) 1 = a write occurred when a previously input word has not been read (must be cleared in software) 0 = no overflow occurred bit 4 pspmode: parallel slave port mode select bit 1 = parallel slave port mode 0 = general purpose i/o mode bit 3 unimplemented: read as '0' bit 2 trise2: direction control bit for pin re2/cs /an7 1 = input 0 = output bit 1 trise1: direction control bit for pin re1/wr /an6 1 = input 0 = output bit 0 trise0: direction control bit for pin re0/rd /an5 1 = input 0 = output legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 09h porte ? ? ? ? ?re2re1re0 ---- -xxx ---- -uuu 89h trise ibf obf ibov pspmode ? porte data direction bits 0000 -111 0000 -111 9fh adcon1 ? ? ? ? ? pcfg2 pcfg1 pcfg0 ---- -000 ---- -000 legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. s haded cells are not used by porte.
? 1998-2013 microchip technology inc. ds30605d-page 37 pic16c63a/65b/73b/74b 5.6 parallel slave port (psp) portd operates as an 8-bit wide parallel slave port (psp), or microprocessor port when control bit psp- mode (trise<4>) is set. in slave mode, it is asyn- chronously readable and writable by the external world, through rd control input pin re0/rd /an5 and wr control input pin re1/wr /an6. it can directly interface to an 8-bit microprocessor data bus. the external microprocessor can read or write the portd latch as an 8-bit latch. setting bit pspmode enables port pin re0/rd /an5 to be the rd input, re1/wr /an6 to be the wr input and re2/cs /an7 to be the cs (chip select) input. for this functionality, the corresponding data direction bits of the trise register (trise<2:0>) must be configured as inputs (set) and the a/d port configuration bits pcfg2:pcfg0 (adcon1<2:0>) must be set, which will configure pins re2:re0 as digital i/o. there are actually two 8-bit latches, one for data out (from the pic ? mcu) and one for data input. the user writes 8-bit data to portd data latch and reads data from the port pin latch (note that they have the same address). in this mode, the trisd register is ignored since the external device is controlling the direction of data flow. a write to the psp occurs when both the cs and wr lines are first detected low. when either the cs or wr lines become high (level triggered), then the input buffer full (ibf) status flag bit (trise<7>) is set on the q4 clock cycle, following the next q2 cycle, to signal the write is complete (figure 5-9). the interrupt flag bit pspif (pir1<7>) is also set on the same q4 clock cycle. ibf can only be cleared by reading the portd input latch. the input buffer overflow (ibov) status flag bit (trise<5>) is set if a second write to the psp is attempted when the previous byte has not been read out of the buffer. a read from the psp occurs when both the cs and rd lines are first detected low. the output buffer full (obf) status flag bit (trise<6>) is cleared immedi- ately (figure 5-10), indicating that the portd latch is waiting to be read by the external bus. when either the cs or rd pin becomes high (level triggered), the inter- rupt flag bit pspif is set on the q4 clock cycle, follow- ing the next q2 cycle, indicating that the read is complete. obf remains low until data is written to portd by the user firmware. when not in psp mode, the ibf and obf bits are held clear. however, if flag bit ibov was previously set, it must be cleared in firmware. an interrupt is generated and latched into flag bit pspif when a read or write operation is completed. pspif must be cleared by the user in firmware and the interrupt can be disabled by clearing the interrupt enable bit pspie (pie1<7>). figure 5-8: portd and porte block diagram (parallel slave port) note: the pic16c63a and pic16c73b do not provide a parallel slave port. the portd, porte, trisd and trise registers are not implemented. data bus wr port rd rdx q d ck en qd en port pin one bit of portd set interrupt flag pspif (pir1<7>) read chip select write rd cs wr ttl ttl ttl ttl note 1: i/o pins have protection diodes to v dd and v ss .
pic16c63a/65b/73b/74b ds30605d-page 38 ? 1998-2013 microchip technology inc. figure 5-9: parallel slave port write waveforms figure 5-10: parallel slave port read waveforms table 5-11: registers associated with parallel slave port q1 q2 q3 q4 cs q1 q2 q3 q4 q1 q2 q3 q4 wr rd ibf obf pspif portd<7:0> q1 q2 q3 q4 cs q1 q2 q3 q4 q1 q2 q3 q4 wr ibf pspif rd obf portd<7:0> address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 08h portd port data latch when written, port pins when read xxxx xxxx uuuu uuuu 09h porte ? ? ? ? ? re2 re1 re0 ---- -xxx ---- -uuu 0bh, 8bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 89h trise ibf obf ibov pspmode ? porte data direction bits 0000 -111 0000 -111 0ch pir1 pspif adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 8ch pie1 pspie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 9fh adcon1 ? ? ? ? ? pcfg2 pcfg1 pcfg0 ---- -000 ---- -000 legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. shaded ce lls are not used by the parallel slave port.
? 1998-2013 microchip technology inc. ds30605d-page 39 pic16c63a/65b/73b/74b 6.0 timer0 module the timer0 module timer/counter has the following fea- tures: ? 8-bit timer/counter ? readable and writable ? 8-bit software programmable prescaler ? internal or external clock select ? interrupt on overflow from ffh to 00h ? edge select for external clock figure 6-1 is a block diagram of the timer0 module and the prescaler shared with the wdt. additional information on the timer0 module is available in the pic ? mid-range mcu family refer- ence manual (ds33023). timer mode is selected by clearing bit t0cs (option_reg<5>). in timer mode, the timer0 module will increment every instruction cycle (without prescaler). if the tmr0 register is written, the incre- ment is inhibited for the following two instruction cycles. the user can work around this by writing an adjusted value to the tmr0 register. counter mode is selected by setting bit t0cs (option_reg<5>). in counter mode, timer0 will increment, either on every rising, or falling edge of pin ra4/t0cki. the incrementing edge is determined by the timer0 source edge select bit t0se (option_reg<4>). clearing bit t0se selects the ris- ing edge. restrictions on the external clock input are discussed in detail in section 6.2. the prescaler is mutually exclusively shared between the timer0 module and the watchdog timer. the prescaler is not readable or writable. section 6.3 details the operation of the prescaler. 6.1 timer0 interrupt the tmr0 interrupt is generated when the tmr0 reg- ister overflows from ffh to 00h. this overflow sets bit t0if (intcon<2>). the interrupt can be masked by clearing bit t0ie (intcon<5>). bit t0if must be cleared in software by the timer0 module interrupt ser- vice routine before re-enabling this interrupt. the tmr0 interrupt cannot awaken the processor from sleep, since the timer is shut-off during sleep. figure 6-1: block diag ram of the timer0/wdt prescaler ra4/t0cki t0se pin m u x clkout (= f osc /4) sync 2 cycles tmr0 reg 8-bit prescaler 8 - to - 1mux m u x m u x watchdog timer psa 0 1 0 1 wdt time-out ps2:ps0 8 note: t0cs, t0se, psa, ps2:ps0 are (option_reg<5:0>). psa wdt enable bit m u x 0 1 0 1 data bus set flag bit t0if on overflow 8 psa t0cs prescaler
pic16c63a/65b/73b/74b ds30605d-page 40 ? 1998-2013 microchip technology inc. 6.2 using timer0 with an external clock the synchronization of t0cki with the internal phase clocks is accomplished by sampling the synchronized input on the q2 and q4 cycles of the internal phase clocks. therefore, it is necessary for t0cki to be high for at least 2 t osc (and a small rc delay of 20 ns) and low for at least 2 t osc (and a small rc delay of 20 ns). refer to the electrical specification for the desired device. 6.3 prescaler there is only one prescaler available which is mutually exclusively shared between the timer0 module and the watchdog timer. a prescaler assignment for the timer0 module means that there is no prescaler for the watch- dog timer, and vice-versa. this prescaler is not read- able or writable (see figure 6-1). the psa and ps2:ps0 bits (option_reg<3:0>) determine the prescaler assignment and prescale ratio. when assigned to the timer0 module, all instructions writing to the tmr0 register (e.g., clrf 1, movwf 1, bsf 1,x ....etc.) will clear the prescaler. when assigned to wdt, a clrwdt instruction will clear the prescaler along with the watchdog timer. the prescaler is not readable or writable. register 6-1: option_reg register note: writing to tmr0, when the prescaler is assigned to timer0, will clear the prescaler count, but will not change the prescaler assignment. r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 rbpu intedg t0cs t0se psa ps2 ps1 ps0 bit 7 bit 0 bit 7 rbpu bit 6 intedg bit 5 t0cs: tmr0 clock source select bit 1 = transition on t0cki pin 0 = internal instruction cycle clock (clkout) bit 4 t0se : tmr0 source edge select bit 1 = increment on high-to-low transition on t0cki pin 0 = increment on low-to-high transition on t0cki pin bit 3 psa: prescaler assignment bit 1 = prescaler is assigned to the wdt 0 = prescaler is assigned to the timer0 module bit 2-0 ps2:ps0: prescaler rate select bits legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 bit value tmr0 rate wdt rate note: to avoid an unintended device reset, the instruction sequence shown in the pic ? mid-range mcu family reference manual (ds33023, section 11.6) must be executed when changing the prescaler assignment from timer0 to the wdt. this sequence must be followed even if the wdt is disabled.
? 1998-2013 microchip technology inc. ds30605d-page 41 pic16c63a/65b/73b/74b table 6-1: registers associated with timer0 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 01h tmr0 timer0 module?s register xxxx xxxx uuuu uuuu 0bh,8bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 81h option_reg rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. shaded cells are not used by timer0.
pic16c63a/65b/73b/74b ds30605d-page 42 ? 1998-2013 microchip technology inc. notes:
? 1998-2013 microchip technology inc. ds30605d-page 43 pic16c63a/65b/73b/74b 7.0 timer1 module the timer1 module is a 16-bit timer/counter consisting of two 8-bit registers (tmr1h and tmr1l), which are readable and writable. the tmr1 register pair (tmr1h:tmr1l) increments from 0000h to ffffh and rolls over to 0000h. the tmr1 interrupt, if enabled, is generated on overflow, which is latched in interrupt flag bit tmr1if (pir1<0>). this interrupt can be enabled/disabled by setting/clearing tmr1 interrupt enable bit tmr1ie (pie1<0>). timer1 can operate in one of two modes: ?as a timer ?as a counter the operating mode is determined by the clock select bit, tmr1cs (t1con<1>). in timer mode, timer1 increments every instruction cycle. in counter mode, it increments on every rising edge of the external clock input. timer1 can be enabled/disabled by setting/clearing control bit tmr1on (t1con<0>). timer1 also has an internal ?reset input?. this reset can be generated by either of the two ccp modules (section 9.0) using the special event trigger. register 7-1 shows the timer1 control register. when the timer1 oscillator is enabled (t1oscen is set), the rc1/t1osi/ccp2 and rc0/t1oso/t1cki pins become inputs. that is, the trisc<1:0> value is ignored, and these pins read as ?0?. additional information on timer modules is available in the pic ? mid-range mcu family reference manual (ds33023). register 7-1: t1con: timer1 control register (address 10h) u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on bit 7 bit 0 bit 7-6 unimplemented: read as '0' bit 5-4 t1ckps1:t1ckps0 : timer1 input clock prescale select bits 11 = 1:8 prescale value 10 = 1:4 prescale value 01 = 1:2 prescale value 00 = 1:1 prescale value bit 3 t1oscen: timer1 oscillator enable control bit 1 = oscillator is enabled 0 = oscillator is shut-off (the oscillator inverter is turned off to eliminate power drain) bit 2 t1sync : timer1 external clock input synchronization control bit tmr1cs = 1: 1 = do not synchronize external clock input 0 = synchronize external clock input tmr1cs = 0: this bit is ignored. timer1 uses the internal clock when tmr1cs = 0. bit 1 tmr1cs: timer1 clock source select bit 1 = external clock from pin rc0/t1oso/t1cki (on the rising edge) 0 = internal clock (f osc /4) bit 0 tmr1on: timer1 on bit 1 = enables timer1 0 = stops timer1 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic16c63a/65b/73b/74b ds30605d-page 44 ? 1998-2013 microchip technology inc. 7.1 timer1 operation in timer mode timer mode is selected by clearing the tmr1cs (t1con<1>) bit. in this mode, the input clock to the timer is f osc /4. the synchronize control bit t1sync (t1con<2>) has no effect since the internal clock is always in sync. 7.2 timer1 operation in synchronized counter mode counter mode is selected by setting bit tmr1cs. in this mode, the timer increments on every rising edge of clock input on pin rc1/t1osi/ccp2, when bit t1oscen is set, or on pin rc0/t1oso/t1cki, when bit t1oscen is cleared. if t1sync is cleared, then the external clock input is synchronized with internal phase clocks. the synchro- nization is done after the prescaler stage. the prescaler stage is an asynchronous ripple counter. in this configuration during sleep mode, timer1 will not increment even if the external clock is present, since the synchronization circuit is shut-off. the prescaler, however, will continue to increment. figure 7-1: timer1 block diagram tmr1h tmr1l t1osc t1sync tmr1cs t1ckps1:t1ckps0 sleep input t1oscen enable oscillator (1) f osc /4 internal clock tmr1on on/off prescaler 1, 2, 4, 8 synchronize det 1 0 0 1 synchronized clock input 2 rc0/t1oso/t1cki rc1/t1osi/ccp2 (2) note 1: when the t1oscen bit is cleared, the inverter is turned off. this eliminates power drain. 2: for the pic16c65b/73b/74b, the schmitt trigger is not implemented in external clock mode. set flag bit tmr1if on overflow tmr1 (2)
? 1998-2013 microchip technology inc. ds30605d-page 45 pic16c63a/65b/73b/74b 7.3 timer1 operation in asynchronous counter mode if control bit t1sync (t1con<2>) is set, the external clock input is not synchronized. the timer continues to increment asynchronous to the internal phase clocks. the timer will continue to run during sleep and can generate an interrupt-on-overflow, which will wake-up the processor. however, special precautions in soft- ware are needed to read/write the timer (section 7.3.1). in asynchronous counter mode, timer1 can not be used as a time-base for capture or compare opera- tions. 7.3.1 reading and writing timer1 in asynchronous counter mode reading tmr1h or tmr1l while the timer is running from an external asynchronous clock will guarantee a valid read (taken care of in hardware). however, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself poses certain problems, since the timer may overflow between the reads. for writes, it is recommended that the user simply stop the timer and write the desired values. a write conten- tion may occur by writing to the timer registers, while the register is incrementing. this may produce an unpredictable value in the timer register. reading the 16-bit value requires some care. exam- ples 12-2 and 12-3 in the pic ? mid-range mcu family reference manual (ds33023) show how to read and write timer1 when it is running in asynchronous mode. 7.4 timer1 oscillator a crystal oscillator circuit is built-in between pins t1osi (input) and t1oso (amplifier output). it is enabled by setting control bit t1oscen (t1con<3>). the oscilla- tor is a low power oscillator rated up to 200 khz. it will continue to run during sleep. it is primarily intended for use with a 32 khz crystal. table 7-1 shows the capacitor selection for the timer1 oscillator. the timer1 oscillator is identical to the lp oscillator. the user must provide a software time delay to ensure proper oscillator start-up. table 7-1: capacitor selection for the timer1 oscillator 7.5 resetting timer1 using a ccp trigger output if the ccp1 or ccp2 module is configured in compare mode to generate a ?special event trigger? (ccp1m3:ccp1m0 = 1011 ), this signal will reset timer1. timer1 must be configured for either timer or synchro- nized counter mode to take advantage of this feature. if timer1 is running in asynchronous counter mode, this reset operation may not work. in the event that a write to timer1 coincides with a spe- cial event trigger from ccp1 or ccp2, the write will take precedence. in this mode of operation, the ccprxh:ccprxl regis- ter pair effectively becomes the period register for timer1. 7.6 resetting of timer1 register pair (tmr1h, tmr1l) tmr1h and tmr1l registers are not reset to 00h on a por, or any other reset, except by the ccp1 and ccp2 special event triggers. t1con register is reset to 00h on a power-on reset or a brown-out reset, which shuts off the timer and leaves a 1:1 prescale. in all other resets, the register is unaffected. 7.7 timer1 prescaler the prescaler counter is cleared on writes to the tmr1h or tmr1l registers. osc type freq c1 c2 lp 32 khz 33 pf 33 pf 100 khz 15 pf 15 pf 200 khz 15 pf 15 pf these values are for design guidance only. crystals tested: 32.768 khz epson c-001r32.768k-a 20 ppm 100 khz epson c-2 100.00 kc-p 20 ppm 200 khz std xtl 200.000 khz 20 ppm note 1: higher capacitance increases the stability of oscillator, but also increases the start-up time. 2: since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appro- priate values of external components. note: the special event triggers from the ccp1 and ccp2 modules will not set interrupt flag bit tmr1if (pir1<0>).
pic16c63a/65b/73b/74b ds30605d-page 46 ? 1998-2013 microchip technology inc. table 7-2: registers associated with timer1 as a timer/counter address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh,8bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1) adif (2) rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 8ch pie1 pspie (1) adie (2) rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 0eh tmr1l holding register for the least significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 0fh tmr1h holding register for the most significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 10h t1con ? ? t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on --00 0000 --uu uuuu legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. shaded cells are not used by the timer1 module. note 1: bits pspie and pspif are reserved on the pic16c63a/73b; always maintain these bits clear. 2: bits adie and adif are reserved on the pic16c63a/65b; always maintain these bits clear.
? 1998-2013 microchip technology inc. ds30605d-page 47 pic16c63a/65b/73b/74b 8.0 timer2 module timer2 is an 8-bit timer with a prescaler and a postscaler. it can be used as the pwm time-base for the pwm mode of the ccp module(s). the tmr2 reg- ister is readable and writable, and is cleared on any device reset. the input clock (f osc /4) has a prescale option of 1:1, 1:4, or 1:16, selected by control bits t2ckps1:t2ckps0 (t2con<1:0>). the timer2 module has an 8-bit period register, pr2. timer2 increments from 00h until it matches pr2 and then resets to 00h on the next increment cycle. pr2 is a readable and writable register. the pr2 register is initialized to ffh upon reset. the match output of tmr2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a tmr2 interrupt (latched in flag bit tmr2if, (pir1<1>)). timer2 can be shut-off by clearing control bit tmr2on (t2con<2>) to minimize power consumption. register 8-1 shows the timer2 control register. additional information on timer modules is available in the pic ? mid-range mcu family reference manual (ds33023). 8.1 timer2 prescaler and postscaler the prescaler and postscaler counters are cleared when any of the following occurs: ? a write to the tmr2 register ? a write to the t2con register ? any device reset (por, bor, mclr reset, or wdt reset) tmr2 is not cleared when t2con is written. 8.2 output of tmr2 the output of tmr2 (before the postscaler) is fed to the ssp module, which optionally uses it to generate the shift clock. figure 8-1: timer2 block diagram register 8-1: t2con: timer2 control register (address 12h) comparator tmr2 sets flag tmr2 reg output (1) reset postscaler prescaler pr2 reg 2 f osc /4 1:1 1:16 1:1, 1:4, 1:16 eq 4 bit tmr2if note 1: tmr2 register output can be software selected by the ssp module as a baud clock. to t2outps3: t2outps0 t2ckps1: t2ckps0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 bit 7 bit 0 bit 7 unimplemented: read as '0' bit 6-3 toutps3:toutps0 : timer2 output postscale select bits 0000 = 1:1 postscale 0001 = 1:2 postscale 0010 = 1:3 postscale ? ? ? 1111 = 1:16 postscale bit 2 tmr2on : timer2 on bit 1 = timer2 is on 0 = timer2 is off bit 1-0 t2ckps1:t2ckps0 : timer2 clock prescale select bits 00 = prescaler is 1 01 = prescaler is 4 1x = prescaler is 16 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic16c63a/65b/73b/74b ds30605d-page 48 ? 1998-2013 microchip technology inc. table 8-1: registers associated with timer2 as a timer/counter address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh,8bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1) adif ( 2 ) rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 8ch pie1 pspie (1) adie ( 2 ) rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 11h tmr2 timer2 module?s register 0000 0000 0000 0000 12h t2con ? toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 92h pr2 timer2 period register 1111 1111 1111 1111 legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. shaded cells are not used by the timer2 module. note 1: bits pspie and pspif are reserved on the pic16c63a/73b; always maintain these bits clear. 2: bits adie and adif are reserved on the pic16c63a/65b; always maintain these bits clear.
? 1998-2013 microchip technology inc. ds30605d-page 49 pic16c63a/65b/73b/74b 9.0 capture/compare/pwm modules each capture/compare/pwm (ccp) module contains a 16-bit register which can operate as a: ? 16-bit capture register ? 16-bit compare register ? pwm master/slave duty cycle register both the ccp1 and ccp2 modules are identical in operation, with the exception being the operation of the special event trigger. table 9-1 and table 9-2 show the resources and interactions of the ccp module(s). in the following sections, the operation of a ccp module is described with respect to ccp1. ccp2 operates the same as ccp1, except where noted. ccp1 module: capture/compare/pwm register1 (ccpr1) is com- prised of two 8-bit registers: ccpr1l (low byte) and ccpr1h (high byte). the ccp1con register controls the operation of ccp1. the special event trigger is generated by a compare match and will reset timer1. ccp2 module: capture/compare/pwm register2 (ccpr2) is com- prised of two 8-bit registers: ccpr2l (low byte) and ccpr2h (high byte). the ccp2con register controls the operation of ccp2. the special event trigger is generated by a compare match and will reset timer1 and start an a/d conversion (if the a/d module is enabled). additional information on ccp modules is available in the pic ? mid-range mcu family reference manual (ds33023) and in ?using the ccp modules? (an594). table 9-1: ccp mode - timer resources required table 9-2: interaction of two ccp modules ccp mode timer resource capture compare pwm timer1 timer1 timer2 ccpx mode ccpy mode interaction capture capture same tmr1 time-base. capture compare the compare should be configured for the special event trigger, which clears tmr1. compare compare the compare(s) should be configured for the special event trigger, which clears tmr1. pwm pwm the pwms will have the same frequency and update rate (tmr2 interrupt). pwm capture none. pwm compare none.
pic16c63a/65b/73b/74b ds30605d-page 50 ? 1998-2013 microchip technology inc. register 9-1: ccp1con register/ccp2con register u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ccpxx ccpxy ccpxm3 ccpxm2 ccpxm1 ccpxm0 bit 7 bit 0 bit 7-6 unimplemented: read as '0' bit 5-4 ccpxx:ccpxy : pwm least significant bits capture mode: unused compare mode: unused pwm mode: these bits are the two lsbs of the pwm duty cycle. the eight msbs are found in ccprxl. bit 3-0 ccpxm3:ccpxm0 : ccpx mode select bits 0000 = capture/compare/pwm disabled (resets ccpx module) 0100 = capture mode, every falling edge 0101 = capture mode, every rising edge 0110 = capture mode, every 4th rising edge 0111 = capture mode, every 16th rising edge 1000 = compare mode, set output on match (ccpxif bit is set) 1001 = compare mode, clear output on match (ccpxif bit is set) 1010 = compare mode, generate software interrupt on match (ccpxif bit is set, ccpx pin is unaffected) 1011 = compare mode, trigger special event (ccpxif bit is set, ccpx pin is unaffected); ccp1 resets tmr1; ccp2 resets tmr1 and starts an a/d conversion (if a/d module is enabled) 11xx =pwm mode legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 1998-2013 microchip technology inc. ds30605d-page 51 pic16c63a/65b/73b/74b 9.1 capture mode in capture mode, ccpr1h:ccpr1l captures the 16-bit value of the tmr1 register when an event occurs on pin rc2/ccp1. an event is defined as one of the fol- lowing and is configured using ccpxcon<3:0>: ? every falling edge ? every rising edge ? every 4th rising edge ? every 16th rising edge an event is selected by control bits ccp1m3:ccp1m0 (ccp1con<3:0>). when a capture is made, the inter- rupt request flag bit ccp1if (pir1<2>) is set. the interrupt flag must be cleared in software. if another capture occurs before the value in register ccpr1 is read, the previous captured value is overwritten by the new captured value. 9.1.1 ccp pin configuration in capture mode, the rc2/ccp1 pin should be config- ured as an input by setting the trisc<2> bit. figure 9-1: capture mode operation block diagram 9.1.2 timer1 mode selection timer1 must be running in timer mode or synchro- nized counter mode for the ccp module to use the capture feature. in asynchronous counter mode, the capture operation may not work. 9.1.3 software interrupt when the capture mode is changed, a false capture interrupt may be generated. the user should keep bit ccp1ie (pie1<2>) clear to avoid false interrupts and should clear the flag bit ccp1if following any such change in operating mode. 9.1.4 ccp prescaler there are four prescaler settings, specified by bits ccp1m3:ccp1m0. whenever the ccp module is turned off, or the ccp module is not in capture mode, the prescaler counter is cleared. any reset will clear the prescaler counter. switching from one capture prescaler to another may generate an interrupt. also, the prescaler counter will not be cleared, therefore, the first capture may be from a non-zero prescaler. example 9-1 shows the recom- mended method for switching between capture pres- calers. this example also clears the prescaler counter and will not generate the ?false? interrupt. example 9-1: changing between capture prescalers clrf ccp1con ; turn ccp module off movlw new_capt_ps ; load the w reg with ; the new prescaler ; move value and ccp on movwf ccp1con ; load ccp1con with this ; value note: if the rc2/ccp1 pin is configured as an output, a write to the port can cause a capture condition. ccpr1h ccpr1l tmr1h tmr1l set flag bit ccp1if (pir1<2>) capture enable q?s ccp1con<3:0> rc2/ccp1 prescaler ? 1, 4, 16 and edge detect pin
pic16c63a/65b/73b/74b ds30605d-page 52 ? 1998-2013 microchip technology inc. 9.2 compare mode in compare mode, the 16-bit ccpr1 register value is constantly compared against the tmr1 register pair value. when a match occurs, the rc2/ccp1 pin is: ? driven high ?driven low ? remains unchanged the action on the pin is based on the value of control bits ccp1m3:ccp1m0 (ccp1con<3:0>). at the same time, interrupt flag bit ccp1if is set. figure 9-2: compare mode operation block diagram 9.2.1 ccp pin configuration the user must configure the rc2/ccp1 pin as an out- put by clearing the trisc<2> bit. 9.2.2 timer1 mode selection timer1 must be running in timer mode or synchro- nized counter mode if the ccp module is using the compare feature. in asynchronous counter mode, the compare operation may not work. 9.2.3 software interrupt mode when generate software interrupt mode is chosen, the ccp1 pin is not affected. the ccpif bit is set, causing a ccp interrupt (if enabled). 9.2.4 special event trigger in this mode, an internal hardware trigger is generated, which may be used to initiate an action. the special event trigger output of ccp1 resets the tmr1 register pair. this allows the ccpr1 register to effectively be a 16-bit programmable period register for timer1. the special event trigger output of ccp2 resets the tmr1 register pair and starts an a/d conversion (if the a/d module is enabled). 9.3 pwm mode (pwm) in pulse width modulation mode, the ccpx pin pro- duces up to a 10-bit resolution pwm output. since the ccp1 pin is multiplexed with the portc data latch, the trisc<2> bit must be cleared to make the ccp1 pin an output. figure 9-3 shows a simplified block diagram of the ccp module in pwm mode. for a step-by-step procedure on how to set up the ccp module for pwm operation, see section 9.3.3. figure 9-3: simplified pwm block diagram note: clearing the ccp1con register will force the rc2/ccp1 compare output latch to the default low level. this is not the portc i/o data latch. ccpr1h ccpr1l tmr1h tmr1l comparator qs r output logic special event trigger set flag bit ccp1if (pir1<2>) match rc2/ccp1 trisc<2> ccp1con<3:0> mode select output enable pin special event trigger will: reset timer1, but not set interrupt flag bit tmr1if (pir1<0>), and set bit go/done (adcon0<2>). note: the special event trigger from the ccp1and ccp2 modules will not set inter- rupt flag bit tmr1if (pir1<0>). note: clearing the ccp1con register will force the ccp1 pwm output latch to the default low level. this is not the portc i/o data latch. ccpr1l ccpr1h (slave) comparator tmr2 comparator pr2 (note 1) r q s duty cycle registers ccp1con<5:4> clear timer, ccp1 pin and latch d.c. trisc<2> rc2/ccp1 note 1: 8-bit timer is concatenated with 2-bit internal q clock, or 2 bits of the prescale, to create 10-bit time-base.
? 1998-2013 microchip technology inc. ds30605d-page 53 pic16c63a/65b/73b/74b a pwm output (figure 9-4) has a time-base (period) and a time that the output stays high (duty cycle). the frequency of the pwm is the inverse of the period (1/period). figure 9-4: pwm output 9.3.1 pwm period the pwm period is specified by writing to the pr2 register. the pwm period can be calculated using the following formula: pwm period = [(pr2) + 1] ? 4 ? t osc ? (tmr2 prescale value) pwm frequency is defined as 1 / [pwm period]. when tmr2 is equal to pr2, the following three events occur on the next increment cycle: ? tmr2 is cleared ? the ccp1 pin is set (exception: if pwm duty cycle = 0%, the ccp1 pin will not be set) ? the pwm duty cycle is latched from ccpr1l into ccpr1h 9.3.2 pwm duty cycle the pwm duty cycle is specified by writing to the ccpr1l register and to the ccp1con<5:4> bits. up to 10-bit resolution is available: the ccpr1l contains the eight msbs and the ccp1con<5:4> contains the two lsbs. this 10-bit value is represented by ccpr1l:ccp1con<5:4>. the following equation is used to calculate the pwm duty cycle in time: pwm duty cycle = (ccpr1l:ccp1con<5:4>) ? t osc ? (tmr2 prescale value) ccpr1l and ccp1con<5:4> can be written to at any time, but the duty cycle value is not latched into ccpr1h until after a match between pr2 and tmr2 occurs (i.e., the period is complete). in pwm mode, ccpr1h is a read-only register. the ccpr1h register and a 2-bit internal latch are used to double buffer the pwm duty cycle. this double buffering is essential for glitchless pwm operation. when the ccpr1h and 2-bit latch match tmr2, con- catenated with an internal 2-bit q clock, or 2 bits of the tmr2 prescaler, the ccp1 pin is cleared. maximum pwm resolution (bits) for a given pwm frequency: 9.3.3 set-up for pwm operation the following steps should be taken when configuring the ccp module for pwm operation: 1. set the pwm period by writing to the pr2 register. 2. set the pwm duty cycle by writing to the ccpr1l register and ccp1con<5:4> bits. 3. make the ccp1 pin an output by clearing the trisc<2> bit. 4. set the tmr2 prescale value and enable timer2 by writing to t2con. 5. configure the ccp1 module for pwm operation. table 9-3: example pwm frequencies and resolutions at 20 mhz note: the timer2 postscaler (see section 8.1) is not used in the determination of the pwm frequency. the postscaler could be used to have a servo update rate at a different fre- quency than the pwm output. period duty cycle tmr2 = pr2 tmr2 = duty cycle tmr2 = pr2 (timer2 reset) (timer2 reset) note: if the pwm duty cycle value is longer than the pwm period, the ccp1 pin will not be cleared. log ( f pwm log(2) f osc ) bits = resolution pwm frequency 1.22 khz 4.88 khz 19.53 khz 78.12 khz 156.3 khz 208.3 khz timer prescaler (1, 4, 16) 16 4 1 1 1 1 pr2 value 0xff 0xff 0xff 0x3f 0x1f 0x17 maximum resolution (bits) 10 10 10 8 7 5.5
pic16c63a/65b/73b/74b ds30605d-page 54 ? 1998-2013 microchip technology inc. table 9-4: registers associated with capture, compare, and timer1 table 9-5: registers associated with pwm and timer2 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh,8bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1) adif (2) rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 0dh pir2 ? ? ? ? ? ? ? ccp2if ---- ---0 ---- ---0 8ch pie1 pspie (1) adie (2) rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 8dh pie2 ? ? ? ? ? ? ? ccp2ie ---- ---0 ---- ---0 87h trisc portc data direction register 1111 1111 1111 1111 0eh tmr1l holding register for the least significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 0fh tmr1h holding register for the most significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 10h t1con ? ? t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on --00 0000 --uu uuuu 15h ccpr1l capture/compare/pwm register1 (lsb) xxxx xxxx uuuu uuuu 16h ccpr1h capture/compare/pwm register1 (msb) xxxx xxxx uuuu uuuu 17h ccp1con ? ? ccp1x ccp1y ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 --00 0000 1bh ccpr2l capture/compare/pwm register2 (lsb) xxxx xxxx uuuu uuuu 1ch ccpr2h capture/compare/pwm register2 (msb) xxxx xxxx uuuu uuuu 1dh ccp2con ? ? ccp2x ccp2y ccp2m3 ccp2m2 ccp2m1 ccp2m0 --00 0000 --00 0000 legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. s haded cells are not used by capture and timer1. note 1: the psp is not implemented on the pic16c63a/73b; always maintain these bits clear. 2: the a/d is not implemented on the pic16c63a/65b; always maintain these bits clear. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh,8bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1) adif (2) rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 0dh pir2 ? ? ? ? ? ? ? ccp2if ---- ---0 ---- ---0 8ch pie1 pspie (1) adie (2) rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 8dh pie2 ? ? ? ? ? ? ? ccp2ie ---- ---0 ---- ---0 87h trisc portc data direction register 1111 1111 1111 1111 11h tmr2 timer2 module?s register 0000 0000 0000 0000 92h pr2 timer2 module?s period register 1111 1111 1111 1111 12h t2con ? toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 15h ccpr1l capture/compare/pwm register1 (lsb) xxxx xxxx uuuu uuuu 16h ccpr1h capture/compare/pwm register1 (msb) xxxx xxxx uuuu uuuu 17h ccp1con ? ? ccp1x ccp1y ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 --00 0000 1bh ccpr2l capture/compare/pwm register2 (lsb) xxxx xxxx uuuu uuuu 1ch ccpr2h capture/compare/pwm register2 (msb) xxxx xxxx uuuu uuuu 1dh ccp2con ? ? ccp2x ccp2y ccp2m3 ccp2m2 ccp2m1 ccp2m0 --00 0000 --00 0000 legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. shaded cells are not used by pwm and timer2. note 1: bits pspie and pspif are reserved on the pic16c63a/73b; always maintain these bits clear. 2: bits adie and adif are reserved on the pic16c63a/65b; always maintain these bits clear.
? 1998-2013 microchip technology inc. ds30605d-page 55 pic16c63a/65b/73b/74b 10.0 synchronous serial port (ssp) module 10.1 ssp module overview the synchronous serial port (ssp) module is a serial interface useful for communicating with other periph- eral or microcontroller devices. these peripheral devices may be serial eeproms, shift registers, dis- play drivers, a/d converters, etc. the ssp module can operate in one of two modes: ? serial peripheral interface (spi) ? inter-integrated circuit (i 2 c) an overview of i 2 c operations and additional informa- tion on the ssp module can be found in the pic ? mid-range mcu family reference manual (ds33023). refer to application note an578, ?use of the ssp module in the i 2 c multi-master environment.? 10.2 spi mode this section contains register definitions and opera- tional characteristics of the spi module. spi mode allows 8 bits of data to be synchronously transmitted and received simultaneously. to accom- plish communication, typically three pins are used: ? serial data out (sdo) rc5/sdo ? serial data in (sdi) rc4/sdi/sda ? serial clock (sck) rc3/sck/scl additionally, a fourth pin may be used when in a slave mode of operation: ? slave select (ss ) ra5/ss /an4 when initializing the spi, several options need to be specified. this is done by programming the appropriate control bits in the sspcon register (sspcon<5:0>) and sspstat<7:6>. these control bits allow the fol- lowing to be specified: ? master mode (sck is the clock output) ? slave mode (sck is the clock input) ? clock polarity (idle state of sck) ? clock edge (output data on rising/falling edge of sck) ? clock rate (master mode only) ? slave select mode (slave mode only) figure 10-1: ssp block diagram (spi mode) to enable the serial port, ssp enable bit, sspen (sspcon<5>) must be set. to reset or reconfigure spi mode, clear bit sspen, re-initialize the sspcon reg- ister, and then set bit sspen. this configures the sdi, sdo, sck, and ss pins as serial port pins. for the pins to behave as the serial port function, they must have their data direction bits (in the trisc register) appro- priately programmed. that is: ? sdi must have trisc<4> set ? sdo must have trisc<5> cleared ? sck (master mode) must have trisc<3> cleared ? sck (slave mode) must have trisc<3> set ?ss must have trisa<5> set ? adcon1 must configure ra5 as a digital i/o pin. . note 1: when the spi is in slave mode with ss pin control enabled (sspcon<3:0> = 0100 ), the spi module will reset if the ss pin is set to v dd . 2: if the spi is used in slave mode with cke = '1', then the ss pin control must be enabled. read write internal data bus rc4/sdi/sda rc5/sdo ra5/ss /an4 rc3/sck/ sspsr reg sspbuf reg sspm3:sspm0 bit0 shift clock ss control enable edge select clock select tmr2 output t cy prescaler 4, 16, 64 trisc<3> 2 edge select 2 4 scl
pic16c63a/65b/73b/74b ds30605d-page 56 ? 1998-2013 microchip technology inc. register 10-1: sspstat: sync serial port status register (address 94h) r/w-0 r/w-0 r-0 r-0 r-0 r-0 r-0 r-0 smp cke d/a psr/w ua bf bit 7 bit 0 bit 7 smp: spi data input sample phase spi master mode: 1 = input data sampled at end of data output time 0 = input data sampled at middle of data output time (microwire ? ) spi slave mode: smp must be cleared when spi is used in slave mode i 2 c mode: this bit must be maintained clear bit 6 cke: spi clock edge select (see figure 10-2, figure 10-3, and figure 10-4) spi mode: ckp = 0: 1 = data transmitted on rising edge of sck (microwire alternate) 0 = data transmitted on falling edge of sck ckp = 1: 1 = data transmitted on falling edge of sck (microwire default) 0 = data transmitted on rising edge of sck i 2 c mode: this bit must be maintained clear bit 5 d/a : data/address bit (i 2 c mode only) 1 = indicates that the last byte received or transmitted was data 0 = indicates that the last byte received or transmitted was address bit 4 p: stop bit (i 2 c mode only). this bit is cleared when the ssp module is disabled, or when the start bit is detected last. sspen is cleared. 1 = indicates that a stop bit has been detected last (this bit is '0' on reset) 0 = stop bit was not detected last bit 3 s: start bit (i 2 c mode only). this bit is cleared when the ssp module is disabled, or when the stop bit is detected last. sspen is cleared. 1 = indicates that a start bit has been detected last (this bit is '0' on reset) 0 = start bit was not detected last bit 2 r/w : read/write bit information (i 2 c mode only). this bit holds the r/w bit information follow- ing the last address match. this bit is only valid from the address match to the next start bit, stop bit, or ack bit. 1 =read 0 =write bit 1 ua: update address (10-bit i 2 c mode only) 1 = indicates that the user needs to update the address in the sspadd register 0 = address does not need to be updated bit 0 bf: buffer full status bit receive (spi and i 2 c modes): 1 = receive complete, sspbuf is full 0 = receive not complete, sspbuf is empty transmit (i 2 c mode only): 1 = transmit in progress, sspbuf is full 0 = transmit complete, sspbuf is empty legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 1998-2013 microchip technology inc. ds30605d-page 57 pic16c63a/65b/73b/74b register 10-2: sspcon: sync se rial port control register (address 14h) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 bit 7 bit 0 bit 7 wcol: write collision flag bit 1 = the sspbuf register was written while still transmitting the previous word (must be cleared in software) 0 = no collision bit 6 sspov: synchronous serial port overflow flag bit in spi mode: 1 = a new byte was received while the sspbuf register is still holding the previous unread data. in case of overflow, the data in sspsr is lost. overflow can only occur in slave mode. the user must read the sspbuf, even if only transmitting data, to avoid setting overflow. in master mode, the overflow bit is not set since each new reception (and trans- mission) is initiated by writing to the sspbuf register. 0 = no overflow in i 2 c mode: 1 = a byte was received while the sspbuf register is still holding the previous unread byte. sspov is a "don?t care" in transmit mode. sspov must be cleared in software in either mode. 0 = no overflow bit 5 sspen: synchronous serial port enable bit. when enabled, the ssp pins must be properly configured as input or output. in spi mode: 1 = enables serial port and configures sck, sdo, and sdi as serial port pins 0 = disables serial port and configures these pins as i/o port pins in i 2 c mode: 1 = enables the serial port and configures the sda and scl pins as serial port pins 0 = disables serial port and configures these pins as i/o port pins bit 4 ckp: clock polarity select bit in spi mode: 1 = idle state for clock is a high level (microwire default) 0 = idle state for clock is a low level (microwire alternate) in i 2 c mode: sck release control 1 = enable clock 0 = holds clock low (clock stretch). (used to ensure data setup time.) bit 3-0 sspm3:sspm0: synchronous serial port mode select bits 0000 = spi master mode, clock = f osc /4 0001 = spi master mode, clock = f osc /16 0010 = spi master mode, clock = f osc /64 0011 = spi master mode, clock = tmr2 output/2 0100 = spi slave mode, clock = sck pin. ss pin control enabled. 0101 = spi slave mode, clock = sck pin. ss pin control disabled. ss can be used as i/o pin. 0110 = i 2 c slave mode, 7-bit address 0111 = i 2 c slave mode, 10-bit address 1011 = i 2 c firmware controlled master mode (slave idle) 1110 = i 2 c slave mode, 7-bit address with start and stop bit interrupts enabled 1111 = i 2 c slave mode, 10-bit address with start and stop bit interrupts enabled legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic16c63a/65b/73b/74b ds30605d-page 58 ? 1998-2013 microchip technology inc. figure 10-2: spi mode timing, master mode figure 10-3: spi mode timing (slave mode with cke = 0) sck (ckp = 0, sdi (smp = 0) sspif bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sdi (smp = 1) sck (ckp = 0, sck (ckp = 1, sck (ckp = 1, sdo bit7 bit7 bit0 bit0 cke = 0) cke = 1) cke = 0) cke = 1) sck (ckp = 0) sdi (smp = 0) sspif bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sck (ckp = 1) sdo bit7 bit0 ss (optional)
? 1998-2013 microchip technology inc. ds30605d-page 59 pic16c63a/65b/73b/74b figure 10-4: spi mode timing (s lave mode with cke = 1) table 10-1: registers associ ated with spi operation sck (ckp = 0) sdi (smp = 0) sspif bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sck (ckp = 1) sdo bit7 bit0 ss address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh,8bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1) adif (2) rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 8ch pie1 pspie (1) adie (2) rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 87h trisc portc data direction register 1111 1111 1111 1111 13h sspbuf synchronous serial port receive buffer/transmit register xxxx xxxx uuuu uuuu 14h sspcon wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 0000 0000 85h trisa ? ? porta data direction register --11 1111 --11 1111 94h sspstat smp cke d/a p s r/w ua bf 0000 0000 0000 0000 legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. shaded cells are not used by the ssp in spi mode. note 1: bits pspie and pspif are reserved on the pic16c63a/73b; always maintain these bits clear. 2: bits adie and adif are reserved on the pic16c63a/65b; always maintain these bits clear.
pic16c63a/65b/73b/74b ds30605d-page 60 ? 1998-2013 microchip technology inc. 10.3 ssp i 2 c operation the ssp module in i 2 c mode fully implements all slave functions, except general call support, and provides interrupts on start and stop bits in hardware to facilitate firmware implementation of the master func- tions. the ssp module implements the standard mode specifications as well as 7-bit and 10-bit addressing. two pins are used for data transfer, the rc3/sck/scl pin, which is the clock (scl), and the rc4/sdi/sda pin, which is the data (sda). the user must configure these pins as inputs or outputs through the trisc<4:3> bits. external pull-up resistors for the scl and sda pins must be provided in the application cir- cuit for proper operation of the i 2 c module. the ssp module functions are enabled by setting ssp enable bit sspen (sspcon<5>). figure 10-5: ssp block diagram (i 2 c mode) the ssp module has five registers for i 2 c operation. these are the: ? ssp control register (sspcon) ? ssp status register (sspstat) ? serial receive/transmit buffer (sspbuf) ? ssp shift register (sspsr) - not directly accessible ? ssp address register (sspadd) the sspcon register allows control of the i 2 c opera- tion. four mode selection bits (sspcon<3:0>) allow one of the following i 2 c modes to be selected: ?i 2 c slave mode (7-bit address) ?i 2 c slave mode (10-bit address) ?i 2 c slave mode (7-bit address), with start and stop bit interrupts enabled to support firmware master mode ?i 2 c slave mode (10-bit address), with start and stop bit interrupts enabled to support firmware master mode ?i 2 c start and stop bit interrupts enabled to support firmware master mode, slave is idle selection of any i 2 c mode with the sspen bit set, forces the scl and sda pins to be open drain, pro- vided these pins are programmed to inputs by setting the appropriate trisc bits. additional information on ssp i 2 c operation can be found in the pic ? mid-range mcu family reference manual (ds33023). 10.3.1 slave mode in slave mode, the scl and sda pins must be config- ured as inputs (trisc<4:3> set). the ssp module will override the input state with the output data when required (slave-transmitter). when an address is matched or the data transfer after an address match is received, the hardware automati- cally generates the acknowledge (ack ) pulse, and then loads the sspbuf register with the received value currently in the sspsr register. there are certain conditions that will cause the ssp module not to give this ack pulse. they include (either or both): a) the buffer full bit bf (sspstat<0>) was set before the transfer was received. b) the overflow bit sspov (sspcon<6>) was set before the transfer was received. in this case, the sspsr register value is not loaded into the sspbuf, but bit sspif (pir1<3>) is set. table 10-2 shows what happens when a data transfer byte is received, given the status of bits bf and sspov. the shaded cells show the condition where user software did not properly clear the overflow condi- tion. flag bit bf is cleared by reading the sspbuf register while bit sspov is cleared through software. the scl clock input must have minimum high and low times for proper operation. the high and low times of the i 2 c specification, as well as the requirement of the ssp module, is shown in timing parameter #100 and parameter #101. read write match detect sspadd reg start and stop bit detect sspbuf reg internal data bus addr match set, reset s, p bits (sspstat reg) rc3/sck/scl rc4/sdi/ shift clock msb lsb sda sspsr reg
? 1998-2013 microchip technology inc. ds30605d-page 61 pic16c63a/65b/73b/74b 10.3.1.1 addressing once the ssp module has been enabled, it waits for a start condition to occur. following the start condi- tion, 8-bits are shifted into the sspsr register. all incoming bits are sampled with the rising edge of the clock (scl) line. the value of register sspsr<7:1> is compared to the value of the sspadd register. the address is compared on the falling edge of the eighth clock (scl) pulse. if the addresses match, and the bf and sspov bits are clear, the following events occur: a) the sspsr register value is loaded into the sspbuf register. b) the buffer full bit, bf is set. c) an ack pulse is generated. d) ssp interrupt flag bit, sspif (pir1<3>) is set (interrupt is generated if enabled) - on the falling edge of the ninth scl pulse. in 10-bit address mode, two address bytes need to be received by the slave (figure 10-7). the five most sig- nificant bits (msbs) of the first address byte specify if this is a 10-bit address. bit r/w (sspstat<2>) must specify a write so the slave device will receive the sec- ond address byte. for a 10-bit address, the first byte would equal ? 1111 0 a9 a8 0 ?, where a9 and a8 are the two msbs of the address. the sequence of events for 10-bit address is as follows, with steps 7 - 9 for slave-transmitter: 1. receive first (high) byte of address (bits sspif, bf, and bit ua (sspstat<1>) are set). 2. update the sspadd register with second (low) byte of address (clears bit ua and releases the scl line). 3. read the sspbuf register (clears bit bf) and clear flag bit sspif. 4. receive second (low) byte of address (bits sspif, bf, and ua are set). 5. update the sspadd register with the first (high) byte of address, if match releases scl line, this will clear bit ua. 6. read the sspbuf register (clears bit bf) and clear flag bit sspif. 7. receive repeated start condition. 8. receive first (high) byte of address (bits sspif and bf are set). 9. read the sspbuf register (clears bit bf) and clear flag bit sspif. table 10-2: data transfer received byte actions status bits as data transfer is received sspsr ?? sspbuf generate ack pulse set bit sspif (ssp interrupt occurs if enabled) bf sspov 0 0 yes yes yes 1 0 no no yes, sspov is set 1 1 no no yes 0 1 no no yes note: shaded cells show the conditions where the user software did not properly clear the overflow condition.
pic16c63a/65b/73b/74b ds30605d-page 62 ? 1998-2013 microchip technology inc. 10.3.1.2 reception when the r/w bit of the address byte is clear and an address match occurs, the r/w bit of the sspstat register is cleared. the received address is loaded into the sspbuf register. when the address byte overflow condition exists, then no acknowledge (ack ) pulse is given. an overflow con- dition is defined as any situation where a received byte in sspbuf is overwritten by the next received byte before it has been read. an overflow has occurred when: a) the buffer full flag bit, bf(sspstat<0>) was set, indicating that the byte in sspbuf was waiting to be read when another byte was received. this sets the sspov flag. b) the overflow flag, sspov (sspcon1<6>) was set. an ssp interrupt is generated for each data transfer byte. flag bit sspif (pir1<3>) must be cleared in soft- ware. the sspstat register is used to determine the status of the byte. figure 10-6: i 2 c waveforms for reception (7-bit address) p 9 8 7 6 5 d0 d1 d2 d3 d4 d5 d6 d7 s a7 a6 a5 a4 a3 a2 a1 sda scl 12 3 4 5 6 7 8 9 12 3 4 56 7 89 123 4 bus master terminates transfer bit sspov is set because the sspbuf register is still full cleared in software sspbuf register is read ack receiving data receiving data d0 d1 d2 d3 d4 d5 d6 d7 ack r/w =0 receiving address sspif (pir1<3>) bf (sspstat<0>) sspov (sspcon<6>) ack ack is not sent
? 1998-2013 microchip technology inc. ds30605d-page 63 pic16c63a/65b/73b/74b 10.3.1.3 transmission when the r/w bit of the incoming address byte is set and an address match occurs, the r/w bit of the sspstat register is set. the received address is loaded into the sspbuf register. the ack pulse will be sent on the ninth bit and pin rc3/sck/scl is held low. the transmit data must be loaded into the sspbuf register, which also loads the sspsr regis- ter. then pin rc3/sck/scl should be enabled by set- ting bit ckp (sspcon<4>). the master must monitor the scl pin prior to asserting another clock pulse. the slave devices may be holding off the master by stretch- ing the clock. the eight data bits are shifted out on the falling edge of the scl input. this ensures that the sda signal is valid during the scl high time (figure 10-7). an ssp interrupt is generated for each data transfer byte. flag bit sspif must be cleared in software, and the sspstat register is used to determine the status of the byte. flag bit sspif is set on the falling edge of the ninth clock pulse. as a slave-transmitter, the ack pulse from the master-receiver is latched on the rising edge of the ninth scl input pulse. if the sda line was high (not ack ), then the data transfer is complete. when the ack is latched by the slave, the slave logic is reset (resets sspstat register) and the slave then monitors for another occurrence of the start bit. if the sda line was low (ack ), the transmit data must be loaded into the sspbuf register, which also loads the sspsr reg- ister. then pin rc3/sck/scl should be enabled by setting bit ckp. figure 10-7: i 2 c waveforms for transmission (7-bit address) sda scl sspif (pir1<3>) bf (sspstat<0>) ckp (sspcon<4>) a7 a6 a5 a4 a3 a2 a1 ack d7 d6 d5 d4 d3 d2 d1 d0 ack transmitting data r/w = 1 receiving address 123456789 123456789 p cleared in software sspbuf is written in software from ssp interrupt service routine set bit after writing to sspbuf s data in sampled scl held low while cpu responds to sspif (the sspbuf must be written to before the ckp bit can be set)
pic16c63a/65b/73b/74b ds30605d-page 64 ? 1998-2013 microchip technology inc. 10.3.2 master mode master mode of operation is supported in firmware using interrupt generation on the detection of the start and stop conditions. the stop (p) and start (s) bits are cleared from a reset, or when the ssp module is disabled. the stop (p) and start (s) bits will toggle based on the start and stop condi- tions. control of the i 2 c bus may be taken when the p bit is set, or the bus is idle and both the s and p bits are clear. in master mode, the scl and sda lines are manipu- lated by clearing the corresponding trisc<4:3> bit(s). the output level is always low, irrespective of the value(s) in portc<4:3>. so when transmitting data, a '1' data bit must have the trisc<4> bit set (input) and a '0' data bit must have the trisc<4> bit cleared (out- put). the same scenario is true for the scl line with the trisc<3> bit. the following events will cause ssp interrupt flag bit, sspif, to be set (an ssp interrupt will occur, if enabled): ? start condition ? stop condition ? data transfer byte transmitted/received master mode of operation can be done with either the slave mode idle (sspm3:sspm0 = 1011 ), or with the slave active. when both master and slave modes are enabled, the software needs to differentiate the source(s) of the interrupt. 10.3.3 multi-master mode in multi-master mode, the interrupt generation on the detection of the start and stop conditions allows the determination of when the bus is free. the stop (p) and start (s) bits are cleared from a reset or when the ssp module is disabled. the stop (p) and start (s) bits will toggle based on the start and stop conditions. control of the i 2 c bus may be taken when bit p (sspstat<4>) is set, or the bus is idle and both the s and p bits clear. when the bus is busy, enabling the ssp interrupt will generate the interrupt when the stop condition occurs. in multi-master operation, the sda line must be moni- tored to see if the signal level is the expected output level. this check only needs to be done when a high level is output. if a high level is expected and a low level is present, the device needs to release the sda and scl lines (set trisc<4:3>). there are two stages where this arbitration can be lost, these are: ? address transfer ? data transfer when the slave logic is enabled, the slave continues to receive. if arbitration was lost during the address trans- fer stage, communication to the device may be in progress. if addressed, an ack pulse will be gener- ated. if arbitration was lost during the data transfer stage, the device will need to re-transfer the data at a later time. table 10-3: registers associated with i 2 c operation address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh, 8bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1) adif (2) rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 8ch pie1 pspie (1) adie (2) rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 13h sspbuf synchronous serial port receive buffer/transmit register xxxx xxxx uuuu uuuu 93h sspadd synchronous serial port (i 2 c mode) address register 0000 0000 0000 0000 14h sspcon wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 0000 0000 94h sspstat smp (3) cke (3) d/a psr/w ua bf 0000 0000 0000 0000 87h trisc portc data direction register 1111 1111 1111 1111 legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. shaded cells are not used by ssp module in i 2 c mode. note 1: pspif and pspie are reserved on the pic16c63a/73b; always maintain these bits clear. 2: adif and adie are reserved on the pic16c63a/65b; always maintain these bits clear. 3: maintain these bits clear in i 2 c mode.
? 1998-2013 microchip technology inc. ds30605d-page 65 pic16c63a/65b/73b/74b 11.0 addressable universal synchronous asynchronous receiver transmitter (usart) the universal synchronous asynchronous receiver transmitter (usart) module is one of the two serial i/o modules. (usart is also known as a serial com- munications interface or sci.) the usart can be con- figured as a full duplex asynchronous system that can communicate with peripheral devices, such as crt ter- minals and personal computers, or it can be configured as a half duplex synchronous system that can commu- nicate with peripheral devices, such as a/d or d/a inte- grated circuits, serial eeproms etc. the usart can be configured in the following modes: ? asynchronous (full duplex) ? synchronous - master (half duplex) ? synchronous - slave (half duplex) bits spen (rcsta<7>) and trisc<7:6> have to be set in order to configure pins rc6/tx/ck and rc7/rx/dt as the universal synchronous asynchro- nous receiver transmitter. register 11-1: txsta: transmit status and control register (address 98h) r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r-1 r/w-0 csrc tx9 txen sync ? brgh trmt tx9d bit 7 bit 0 bit 7 csrc: clock source select bit asynchronous mode: don?t care synchronous mode: 1 = master mode (clock generated internally from brg) 0 = slave mode (clock from external source) bit 6 tx9: 9-bit transmit enable bit 1 = selects 9-bit transmission 0 = selects 8-bit transmission bit 5 txen: transmit enable bit 1 = transmit enabled 0 = transmit disabled note: sren/cren overrides txen in sync mode. bit 4 sync: usart mode select bit 1 = synchronous mode 0 = asynchronous mode bit 3 unimplemented: read as '0' bit 2 brgh: high baud rate select bit asynchronous mode: 1 =high speed 0 = low speed synchronous mode: unused in this mode bit 1 trmt: transmit shift register status bit 1 = tsr empty 0 = tsr full bit 0 tx9d: 9th bit of transmit data. can be parity bit. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic16c63a/65b/73b/74b ds30605d-page 66 ? 1998-2013 microchip technology inc. register 11-2: rcsta: receive status and control register (address 18h) r/w-0 r/w-0 r/w-0 r/w-0 u-0 r-0 r-0 r-x spen rx9 sren cren ? ferr oerr rx9d bit 7 bit 0 bit 7 spen: serial port enable bit 1 = serial port enabled (configures rc7/rx/dt and rc6/tx/ck pins as serial port pins) 0 = serial port disabled bit 6 rx9: 9-bit receive enable bit 1 = selects 9-bit reception 0 = selects 8-bit reception bit 5 sren: single receive enable bit asynchronous mode: don?t care synchronous mode - master: 1 = enables single receive 0 = disables single receive this bit is cleared after reception is complete. synchronous mode - slave: don?t care bit 4 cren: continuous receive enable bit asynchronous mode: 1 = enables continuous receive 0 = disables continuous receive synchronous mode: 1 = enables continuous receive until enable bit cren is cleared (cren overrides sren) 0 = disables continuous receive bit 3 unimplemented: read as '0' bit 2 ferr: framing error bit 1 = framing error (can be updated by reading rcreg register and receive next valid byte) 0 = no framing error bit 1 oerr: overrun error bit 1 = overrun error (can be cleared by clearing bit cren) 0 = no overrun error bit 0 rx9d: 9th bit of received data. (can be parity bit. calculated by firmware.) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 1998-2013 microchip technology inc. ds30605d-page 67 pic16c63a/65b/73b/74b 11.1 usart baud rate generator (brg) the brg supports both the asynchronous and syn- chronous modes of the usart. it is a dedicated 8-bit baud rate generator. the spbrg register controls the period of a free running 8-bit timer. in asynchronous mode, bit brgh (txsta<2>) also controls the baud rate. in synchronous mode, bit brgh is ignored. table 11-1 shows the formula for computation of the baud rate for different usart modes, which only apply in master mode (internal clock). given the desired baud rate and fosc, the nearest inte- ger value for the spbrg register can be calculated using the formula in table 11-1. from this, the error in baud rate can be determined. it may be advantageous to use the high baud rate (brgh = 1) even for slower baud clocks. this is because the f osc /(16(x + 1)) equation can reduce the baud rate error in some cases. writing a new value to the spbrg register causes the brg timer to be reset (or cleared). this ensures the brg does not wait for a timer overflow before output- ting the new baud rate. 11.1.1 sampling the data on the rc7/rx/dt pin is sampled three times near the center of each bit time by a majority detect cir- cuit to determine if a high or a low level is present at the rx pin. table 11-1: baud rate formula table 11-2: registers associated with baud rate generator sync brgh = 0 (low speed) brgh = 1 (high speed) 0 1 (asynchronous) baud rate = f osc /(64(spbrg+1)) (synchronous) baud rate = f osc /(4(spbrg+1)) baud rate = f osc /(16(spbrg+1)) n/a address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 98h txsta csrc tx9 txen sync ?brgh trmt tx9d 0000 -010 0000 -010 18h rcsta spen rx9 sren cren ? ferr oerr rx9d 0000 -00x 0000 -00x 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented, read as '0 '. shaded cells are not used by the brg.
pic16c63a/65b/73b/74b ds30605d-page 68 ? 1998-2013 microchip technology inc. 11.2 usart asynchronous mode in this mode, the usart uses standard non- return-to-zero (nrz) format (one start bit, eight or nine data bits, and one stop bit). the most common data format is 8 bits. an on-chip, dedicated, 8-bit baud rate generator can be used to derive standard baud rate frequencies from the oscillator. the usart trans- mits and receives the lsb first. the usart?s transmit- ter and receiver are functionally independent, but use the same data format and baud rate. the baud rate generator produces a clock, either x16 or x64 of the bit shift rate, depending on bit brgh (txsta<2>). parity is not supported by the hardware, but can be imple- mented in software (and stored as the ninth data bit). asynchronous mode is stopped during sleep. asynchronous mode is selected by clearing bit sync (txsta<4>). the usart asynchronous module consists of the fol- lowing important elements: ? baud rate generator ? sampling circuit ? asynchronous transmitter ? asynchronous receiver 11.2.1 usart asynchronous transmitter the usart transmitter block diagram is shown in figure 11-1. the heart of the transmitter is the transmit (serial) shift register (tsr). the shift register obtains its data from the read/write transmit buffer, txreg. the txreg register is loaded with data in software. the tsr register is not loaded until the stop bit has been transmitted from the previous load. as soon as the stop bit is transmitted, the tsr is loaded with new data from the txreg register (if available). once the txreg register transfers the data to the tsr register (occurs in one t cy ), the txreg register is empty and the usart transmit flag bit txif (pir1<4>) is set. this interrupt can be enabled/disabled by setting/clear- ing the usart transmit enable bit txie (pie1<4>). the flag bit txif will be set, regardless of the state of enable bit txie and cannot be cleared in software. it will reset only when new data is loaded into the txreg register. while flag bit txif indicates the status of the txreg register, another bit trmt (txsta<1>) shows the status of the tsr register. status bit trmt is a read only bit, which is set when the tsr register is empty. no interrupt logic is tied to this bit, so the user has to poll this bit in order to determine if the tsr register is empty. transmission is enabled by setting enable bit txen (txsta<5>). the actual transmission will not occur until the txreg register has been loaded with data and the baud rate generator (brg) has produced a shift clock (figure 11-2). the transmission can also be started by first loading the txreg register and then setting enable bit txen. normally, when transmission is first started, the tsr register is empty. at that point, transfer to the txreg register will result in an immedi- ate transfer to tsr, resulting in an empty txreg. a back-to-back transfer is thus possible (figure 11-3). clearing enable bit txen during a transmission will cause the transmission to be aborted and will reset the transmitter. as a result, the rc6/tx/ck pin will revert to hi-impedance. in order to select 9-bit transmission, transmit bit tx9 (txsta<6>) should be set and the ninth bit should be written to tx9d (txsta<0>). the ninth bit must be written before writing the 8-bit data to the txreg reg- ister. this is because a data write to the txreg regis- ter can result in an immediate transfer of the data to the tsr register (if the tsr is empty). in such a case, an incorrect ninth data bit may be loaded in the tsr register. figure 11-1: usart transmit block diagram note 1: the tsr register is not mapped in data memory, so it is not available to the user. 2: flag bit txif is set when enable bit txen is set. txif is cleared by loading txreg. txif txie interrupt txen baud rate clk spbrg baud rate generator tx9d msb lsb data bus txreg register tsr register (8) 0 tx9 trmt spen rc6/tx/ck pin pin buffer and control 8 ?????????
? 1998-2013 microchip technology inc. ds30605d-page 69 pic16c63a/65b/73b/74b steps to follow when setting up an asynchronous transmission: 1. initialize the spbrg register for the appropriate baud rate. if a high speed baud rate is desired, set bit brgh. (section 11.1) 2. enable the asynchronous serial port by clearing bit sync and setting bit spen. 3. if interrupts are desired, set interrupt enable bits txie (pie1<4>), peie (intcon<6>), and gie (intcon<7>), as required. 4. if 9-bit transmission is desired, then set transmit bit tx9. 5. enable the transmission by setting bit txen, which will also set flag bit txif. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 7. load data to the txreg register (starts trans- mission). figure 11-2: asynchronous master transmission figure 11-3: asynchronous master transmission (back to back) table 11-3: registers associated with asynchronous transmission address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh,8bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1) adif ( 2 ) rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 18h rcsta spen rx9 sren cren ? ferr oerr rx9d 0000 -00x 0000 -00x 19h txreg usart transmit register 0000 0000 0000 0000 8ch pie1 pspie (1) adie (2 ) rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 98h txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: u = unchanged, x = unknown, - = unimplemented locations read as '0'. shaded cells are not used fo r asynchronous transmission. note 1: bits pspie and pspif are reserved on the pic16c63a/73b; always maintain these bits clear. 2: bits adie and adif are reserved on the pic16c63a/65b; always maintain these bits clear. word 1 stop bit word 1 transmit shift reg start bit bit 0 bit 1 bit 7/8 write to txreg word 1 brg output (shift clock) rc6/tx/ck (pin) txif bit (transmit buffer reg. empty flag) trmt bit (transmit shift reg. empty flag) transmit shift reg. write to txreg brg output (shift clock) rc6/tx/ck (pin) txif bit (interrupt reg. flag) trmt bit (transmit shift reg. empty flag) word 1 word 2 word 1 word 2 start bit stop bit start bit transmit shift reg. word 1 word 2 bit 0 bit 1 bit 7/8 bit 0 note: this timing diagram shows two consecutive transmissions.
pic16c63a/65b/73b/74b ds30605d-page 70 ? 1998-2013 microchip technology inc. 11.2.2 usart asynchronous receiver the receiver block diagram is shown in figure 11-4. the data is received on the rc7/rx/dt pin and drives the data recovery block. the data recovery block is actually a high speed shifter operating at x16 times the baud rate, whereas the main receive serial shifter oper- ates at the bit rate or at f osc . once asynchronous mode is selected, reception is enabled by setting bit cren (rcsta<4>). the heart of the receiver is the receive (serial) shift reg- ister (rsr). after sampling the stop bit, the received data in the rsr is transferred to the rcreg register (if it is empty). if the transfer is complete, usart receive flag bit rcif (pir1<5>) is set. this interrupt can be enabled/disabled by setting/clearing the usart receive enable bit rcie (pie1<5>). flag bit rcif is a read only bit, which is cleared by the hardware. it is cleared when the rcreg register has been read and is empty. the rcreg is a double buff- ered register, i.e., it is a two-deep fifo. it is possible for two bytes of data to be received and transferred to the rcreg fifo and a third byte to begin shifting to the rsr register. on the detection of the stop bit of the third byte, if the rcreg register is still full, then overrun error bit oerr (rcsta<1>) will be set. the word in the rsr will be lost. the rcreg register can be read twice to retrieve the two bytes in the fifo. overrun bit oerr has to be cleared in software. this is done by resetting the receive logic (cren is cleared and then set). if bit oerr is set, transfers from the rsr register to the rcreg register are inhibited, and no further data will be received; therefore, it is essential to clear error bit oerr if it is set. framing error bit ferr (rcsta<2>) is set if a stop bit is detected as clear. bit ferr and the 9th receive bit are buffered the same way as the receive data. reading the rcreg will load bits rx9d and ferr with new values, there- fore, it is essential for the user to read the rcsta reg- ister before reading the rcreg register, in order not to lose the old ferr and rx9d information. figure 11-4: usart receive block diagram x64 baud rate clk spbrg baud rate generator rc7/rx/dt pin buffer and control spen data recovery cren oerr ferr rsr register msb lsb rx9d rcreg register fifo interrupt rcif rcie data bus 8 ? 64 ? 16 or stop start (8) 7 1 0 rx9 ??????? f osc
? 1998-2013 microchip technology inc. ds30605d-page 71 pic16c63a/65b/73b/74b steps to follow when setting up an asynchronous reception: 1. initialize the spbrg register for the appropriate baud rate. if a high speed baud rate is desired, set bit brgh. (section 11.1). 2. enable the asynchronous serial port by clearing bit sync, and setting bit spen. 3. if interrupts are desired, set interrupt enable bits rcie (pie1<5>), peie (intcon<6>), and gie (intcon<7>), as required. 4. if 9-bit reception is desired, then set bit rx9. 5. enable the reception by setting bit cren. 6. flag bit rcif will be set when reception is com- plete and an interrupt will be generated if enable bit rcie was set. 7. read the rcsta register to get the ninth bit (if enabled) and determine if any error occurred during reception. 8. read the 8-bit received data by reading the rcreg register. 9. if any error occurred, clear the error by clearing enable bit cren. figure 11-5: asynchronous reception table 11-4: registers associated with asynchronous reception start bit bit7/8 bit1 bit0 bit7/8 bit0 stop bit start bit start bit bit7/8 stop bit rx (pin) reg rcv buffer reg rcv shift read rcv buffer reg rcreg rcif (interrupt flag) oerr bit cren word 1 rcreg word 2 rcreg stop bit note: this timing diagram shows three words appearing on the rx input. the rcreg (receive buffer) is read after the third word, causing the oerr (overrun) bit to be set. an overrun error indicates an error in user?s firmware. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh,8bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1) adif (2) rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 18h rcsta spen rx9 sren cren ? ferr oerr rx9d 0000 -00x 0000 -00x 1ah rcreg usart receive register 0000 0000 0000 0000 8ch pie1 pspie (1) adie (2) rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 98h txsta csrc tx9 txen sync ?brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: u = unchanged, x = unknown, - = unimplemented locations read as '0'. shaded cells are not used fo r asynchronous reception. note 1: bits pspie and pspif are reserved on the pic16c73/73a/76; always maintain these bits clear. 2: bits adie and adif are reserved on the pic16c63a/65b; always maintain these bits clear.
pic16c63a/65b/73b/74b ds30605d-page 72 ? 1998-2013 microchip technology inc. 11.2.3 usart synchronous master mode in synchronous master mode, the data is transmitted in a half-duplex manner, i.e., transmission and reception do not occur at the same time. when transmitting data, the reception is inhibited and vice versa. synchronous mode is entered by setting bit sync (txsta<4>). in addition, enable bit spen (rcsta<7>) is set in order to configure the rc6/tx/ck and rc7/rx/dt i/o pins to ck (clock) and dt (data) lines, respectively. the master mode indicates that the processor transmits the master clock on the ck line. the master mode is entered by setting bit csrc (txsta<7>). 11.2.4 usart synchronous master transmission the usart transmitter block diagram is shown in figure 11-1. the heart of the transmitter is the transmit (serial) shift register (tsr). the shift register obtains its data from the read/write transmit buffer register, txreg. the txreg register is loaded with data in software. the tsr register is not loaded until the last bit has been transmitted from the previous load. as soon as the last bit is transmitted, the tsr is loaded with new data from the txreg (if available). once the txreg register transfers the data to the tsr register (occurs in one t cycle ), the txreg is empty and inter- rupt flag bit txif (pir1<4>) is set. the interrupt can be enabled/disabled by setting/clearing enable bit txie (pie1<4>). flag bit txif will be set, regardless of the state of enable bit txie and cannot be cleared in soft- ware. it will reset only when new data is loaded into the txreg register. while flag bit txif indicates the status of the txreg register, another bit trmt (txsta<1>) shows the status of the tsr register. trmt is a read only bit which is set when the tsr is empty. no inter- rupt logic is tied to this bit, so the user has to poll this bit in order to determine if the tsr register is empty. the tsr is not mapped in data memory, so it is not available to the user. transmission is enabled by setting enable bit txen (txsta<5>). the actual transmission will not occur until the txreg register has been loaded with data. the first data bit will be shifted out on the next available rising edge of the clock on the ck line. data out is sta- ble around the falling edge of the synchronous clock (figure 11-6). the transmission can also be started by first loading the txreg register and then setting bit txen (figure 11-7). this is advantageous when slow baud rates are selected, since the brg is kept in reset when bits txen, cren and sren are clear. setting enable bit txen will start the brg, creating a shift clock immediately. normally, when transmission is first started, the tsr register is empty, so a transfer to the txreg register will result in an immediate transfer to tsr resulting in an empty txreg. back-to-back transfers are possible. clearing enable bit txen, during a transmission, will cause the transmission to be aborted and will reset the transmitter. the dt and ck pins will revert to hi-impedance. if either bit cren, or bit sren is set during a transmission, the transmission is aborted and the dt pin reverts to a hi-impedance state (for a recep- tion). the ck pin will remain an output if bit csrc is set (internal clock). the transmitter logic, however, is not reset, although it is disconnected from the pins. in order to reset the transmitter, the user has to clear bit txen. if bit sren is set (to interrupt an on-going transmission and receive a single word), then after the single word is received, bit sren will be cleared and the serial port will revert back to transmitting, since bit txen is still set. the dt line will immediately switch from hi-impedance receive mode to transmit and start driv- ing. to avoid this, bit txen should be cleared. in order to select 9-bit transmission, the tx9 (txsta<6>) bit should be set and the ninth bit should be written to bit tx9d (txsta<0>). the ninth bit must be written before writing the 8-bit data to the txreg register. this is because a data write to the txreg can result in an immediate transfer of the data to the tsr register (if the tsr is empty). if the tsr was empty and the txreg was written before writing the ?new? tx9d, the ?present? value of bit tx9d is loaded. steps to follow when setting up a synchronous master transmission: 1. initialize the spbrg register for the appropriate baud rate (section 11.1). 2. enable the synchronous master serial port by setting bits sync, spen and csrc. 3. if interrupts are desired, set interrupt enable bits txie (pie1<4>), peie (intcon<6>), and gie (intcon<7>), as required. 4. if 9-bit transmission is desired, set bit tx9. 5. enable the transmission by setting bit txen. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 7. start transmission by loading data to the txreg register.
? 1998-2013 microchip technology inc. ds30605d-page 73 pic16c63a/65b/73b/74b table 11-5: registers associated wi th synchronous master transmission figure 11-6: synchronous transmission figure 11-7: synchronous tr ansmission (through txen) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh,8bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1) adif ( 2 ) rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 18h rcsta spen rx9 sren cren ? ferr oerr rx9d 0000 -00x 0000 -00x 19h txreg usart transmit register 0000 0000 0000 0000 8ch pie1 pspie (1) adie ( 2 ) rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 98h txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: u = unchanged, x = unknown, - = unimplemented, read as '0'. shaded cells are not used for sy nchronous master transmission. note 1: bits pspie and pspif are reserved on the pic16c63a/73b; always maintain these bits clear. 2: bits adie and adif are reserved on the pic16c63a/65b; always maintain these bits clear. bit 0 bit 1 bit 7 word 1 q1q2 q3q4 q1 q2q3 q4 q1 q2q3 q4 q1 q2q3 q4 q1 q2 q3q4 q3q4 q1q2 q3q4 q1q2 q3q4 q1q2 q3 q4 q1 q2q3 q4 q1 q2q3 q4 q1 q2q3 q4 bit 2 bit 0 bit 1 bit 7 rc7/rx/dt rc6/tx/ck write to txreg reg txif bit (interrupt flag) trmt txen bit '1' '1' note: sync master mode; spbrg = '0'. continuous transmission of two 8-bit words. word 2 trmt bit write word1 write word2 pin pin rc7/rx/dt pin rc6/tx/ck pin write to txreg reg txif bit trmt bit bit0 bit1 bit2 bit6 bit7 txen bit
pic16c63a/65b/73b/74b ds30605d-page 74 ? 1998-2013 microchip technology inc. 11.2.5 usart synchronous master reception once synchronous mode is selected, reception is enabled by setting either enable bit sren (rcsta<5>), or enable bit cren (rcsta<4>). data is sampled on the rc7/rx/dt pin on the falling edge of the clock. if enable bit sren is set, then only a single word is received. if enable bit cren is set, the recep- tion is continuous until cren is cleared. if both bits are set, cren takes precedence. after clocking the last bit, the received data in the receive shift register (rsr) is transferred to the rcreg register (if it is empty). when the transfer is complete, interrupt flag bit rcif (pir1<5>) is set. the interrupt from the usart can be enabled/disabled by setting/clearing enable bit rcie (pie1<5>). flag bit rcif is a read only bit, which is reset by the hardware. in this case, it is reset when the rcreg register has been read and is empty. the rcreg is a double buffered register, i.e., it is a two-deep fifo. it is possible for two bytes of data to be received and transferred to the rcreg fifo and a third byte to begin shifting into the rsr register. on the clocking of the last bit of the third byte, if the rcreg register is still full, then overrun error bit oerr (rcsta<1>) is set. the word in the rsr will be lost. the rcreg register can be read twice to retrieve the two bytes in the fifo. bit oerr has to be cleared in software (by clearing bit cren). if bit oerr is set, transfers from the rsr to the rcreg are inhibited, and no further data will be received; therefore, it is essential to clear bit oerr if it is set. the ninth receive bit is buffered the same way as the receive data. read- ing the rcreg register will load bit rx9d with a new value, therefore it is essential for the user to read the rcsta register before reading rcreg in order not to lose the old rx9d information. steps to follow when setting up a synchronous master reception: 1. initialize the spbrg register for the appropriate baud rate. (section 11.1) 2. enable the synchronous master serial port by setting bits sync, spen, and csrc. 3. ensure bits cren and sren are clear. 4. if interrupts are desired, set interrupt enable bits rcie (pie1<5>), peie (intcon<6>), and gie (intcon<7>), as required. 5. if 9-bit reception is desired, then set bit rx9. 6. if a single reception is required, set bit sren. for continuous reception set bit cren. 7. interrupt flag bit rcif will be set when reception is complete and an interrupt will be generated if enable bit rcie was set. 8. read the rcsta register to get the ninth bit (if enabled) and determine if any error occurred during reception. 9. read the 8-bit received data by reading the rcreg register. 10. if any error occurred, clear the error by clearing bit cren.
? 1998-2013 microchip technology inc. ds30605d-page 75 pic16c63a/65b/73b/74b table 11-6: registers associated with synchronous master reception figure 11-8: synchronous rece ption (master mode, sren) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh,8bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1) adif ( 2 ) rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 18h rcsta spen rx9 sren cren ? ferr oerr rx9d 0000 -00x 0000 -00x 1ah rcreg usart receive register 0000 0000 0000 0000 8ch pie1 pspie (1) adie ( 2 ) rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 98h txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: u = unchanged, x = unknown, - = unimplemented, read as '0'. shaded cells are not used for sy nchronous master reception. note 1: bits pspie and pspif are reserved on the pic16c63a/73b; always maintain these bits clear. 2: bits adie and adif are reserved on the pic16c63a/65b; always maintain these bits clear. cren bit rc7/rx/dt pin rc6/tx/ck pin write to bit sren sren bit rcif bit (interrupt) read rxreg note: timing diagram demonstrates sync master mode with bit sren = '1' and bit brg = '0'. q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q2 q1 q2 q3 q4q1 q2 q3 q4 q1 q2 q3 q4q1 q2 q3 q4 q1 q2 q3 q4q1 q2 q3 q4 q1 q2 q3 q4 '0' bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 '0' q1 q2 q3 q4
pic16c63a/65b/73b/74b ds30605d-page 76 ? 1998-2013 microchip technology inc. 11.3 usart synchronous slave mode synchronous slave mode differs from the master mode in the fact that the shift clock is supplied externally at the rc6/tx/ck pin (instead of being supplied internally in master mode). this allows the device to transfer or receive data while in sleep mode. slave mode is entered by clearing bit csrc (txsta<7>). 11.3.1 usart synchronous slave transmit the operation of the synchronous master and slave modes are identical, except in the case of the sleep mode. if two words are written to the txreg and then the sleep instruction is executed, the following will occur: a) the first word will immediately transfer to the tsr register and transmit. b) the second word will remain in txreg register. c) flag bit txif will not be set. d) when the first word has been shifted out of tsr, the txreg register will transfer the second word to the tsr and flag bit txif will now be set. e) if interrupt enable bits txie and peie are set, the interrupt will wake the chip from sleep. if gie is set, the program will branch to the inter- rupt vector (0004h), otherwise execution will resume from the instruction following the sleep instruction. steps to follow when setting up a synchronous slave transmission: 1. enable the synchronous slave serial port by set- ting bits sync and spen and clearing bit csrc. 2. clear bits cren and sren. 3. if interrupts are desired, set interrupt enable bits txie (pie1<4>), peie (intcon<6>), and gie (intcon<7>), as required. 4. if 9-bit transmission is desired, set bit tx9. 5. enable the transmission by setting enable bit txen. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 7. start transmission by loading data to the txreg register. 11.3.2 usart synchronous slave reception the operation of the synchronous master and slave modes is identical, except in the case of the sleep mode. also, bit sren is a ?don't care? in slave mode. if receive is enabled by setting bit cren prior to the sleep instruction, a word may be received during sleep. on completely receiving the word, the rsr register will transfer the data to the rcreg register. if interrupt enable bits rcie and peie are set, the inter- rupt generated will wake the chip from sleep. if the global interrupt is enabled, the program will branch to the interrupt vector (0004h), otherwise execution will resume from the instruction following the sleep instruction. steps to follow when setting up a synchronous slave reception: 1. enable the synchronous master serial port by setting bits sync and spen and clearing bit csrc. 2. if interrupts are desired, set interrupt enable bits rcie (pie1<5>), peie (intcon<6>), and gie (intcon<7>), as required. 3. if 9-bit reception is desired, set bit rx9. 4. to enable reception, set enable bit cren. 5. flag bit rcif will be set when reception is com- plete and an interrupt will be generated, if enable bit rcie was set. 6. read the rcsta register to get the ninth bit (if enabled) and determine if any error occurred during reception. 7. read the 8-bit received data by reading the rcreg register. 8. if any error occurred, clear the error by clearing bit cren.
? 1998-2013 microchip technology inc. ds30605d-page 77 pic16c63a/65b/73b/74b table 11-7: registers associated with synchronous slave transmission table 11-8: registers associated with synchronous slave reception address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh,8bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1) adif ( 2 ) rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 18h rcsta spen rx9 sren cren ? ferr oerr rx9d 0000 -00x 0000 -00x 19h txreg usart transmit register 0000 0000 0000 0000 8ch pie1 pspie (1) adie ( 2 ) rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 98h txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: u = unchanged, x = unknown, - = unimplemented, read as '0'. shaded cells are not used for synchronous slave transmission. note 1: bits pspie and pspif are reserved on the pic16c63a/73b; always maintain these bits clear. 2: bits adie and adif are reserved on the pic16c63a/65b; always maintain these bits clear. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh,8bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1) adif ( 2 ) rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 18h rcsta spen rx9 sren cren ? ferr oerr rx9d 0000 -00x 0000 -00x 1ah rcreg usart receive register 0000 0000 0000 0000 8ch pie1 pspie (1) adie ( 2 ) rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 98h txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: u = unchanged, x = unknown, - = unimplemented, read as '0'. shaded cells are not used for synchronous slave reception. note 1: bits pspie and pspif are reserved on the pic16c63a/73b; always maintain these bits clear. 2: bits adie and adif are reserved on the pic16c63a/65b; always maintain these bits clear.
pic16c63a/65b/73b/74b ds30605d-page 78 ? 1998-2013 microchip technology inc. notes:
? 1998-2013 microchip technology inc. ds30605d-page 79 pic16c63a/65b/73b/74b 12.0 analog-to-digital converter (a/d) module the 8-bit analog-to-digital (a/d) converter module has five inputs for the pic16c73b and eight for the pic16c74b. the a/d allows conversion of an analog input signal to a corresponding 8-bit digital number. the output of the sample and hold is the input into the converter, which generates the result via successive approximation. the analog reference voltage is software selectable to either the device?s positive supply voltage (v dd ), or the voltage level on the ra3/an3/v ref pin. the a/d converter has a unique feature of being able to operate while the device is in sleep mode. to oper- ate in sleep, the a/d conversion clock must be derived from the a/d?s internal rc oscillator. the a/d module has three registers. these registers are: ? a/d result register (adres) ? a/d control register 0 (adcon0) ? a/d control register 1 (adcon1) the adcon0 register, shown in register 12-1, con- trols the operation of the a/d module. the adcon1 register, shown in register 12-2, configures the func- tions of the port pins. the port pins can be configured as analog inputs (ra3 can also be a voltage reference), or as digital i/o. additional information on using the a/d module can be found in the pic ? mid-range mcu family reference manual (ds33023) and in application note, an546. register 12-1: adcon0 register (address 1fh) note: the pic16c63a and pic16c65b do not include a/d modules. adcon0, adcon1 and adres registers are not imple- mented. adif and adie bits are reserved and should be maintained clear. r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 adcs1 adcs0 chs2 chs1 chs0 go/done ?adon bit 7 bit 0 bit 7-6 adcs1:adcs0: a/d conversion clock select bits 00 =f osc /2 01 =f osc /8 10 =f osc /32 11 =f rc (clock derived from the internal a/d module rc oscillator) bit 5-3 chs2:chs0: analog channel select bits 000 = channel 0, (ra0/an0) 001 = channel 1, (ra1/an1) 010 = channel 2, (ra2/an2) 011 = channel 3, (ra3/an3) 100 = channel 4, (ra5/an4) 101 = channel 5, (re0/an5) (1) 110 = channel 6, (re1/an6) (1) 111 = channel 7, (re2/an7) (1) bit 2 go/done : a/d conversion status bit if adon = 1: 1 = a/d conversion in progress (setting this bit starts the a/d conversion) 0 = a/d conversion not in progress (this bit is automatically cleared by hardware when the a/d conversion is complete) bit 1 unimplemented: read as '0' bit 0 adon: a/d on bit 1 = a/d converter module is operating 0 = a/d converter module is shut-off and consumes no operating current note 1: a/d channels 5, 6 and 7 are implemented on the pic16c74b only. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic16c63a/65b/73b/74b ds30605d-page 80 ? 1998-2013 microchip technology inc. register 12-2: adcon1 register (address 9fh) u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 ? ? ? ? ? pcfg2 pcfg1 pcfg0 bit 7 bit 0 bit 7-3 unimplemented: read as '0' bit 2-0 pcfg2:pcfg0: a/d port configuration control bits note 1: re0, re1 and re2 are implemented on the pic16c74b only. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown a = analog input d = digital i/o pcfg2:pcfg0 ra0 ra1 ra2 ra5 ra3 re0 (1) re1 (1) re2 (1) v ref 000 aaaa a aaav dd 001 aaaav ref aaara3 010 aaaa a dddv dd 011 aaaav ref dddra3 100 aadd a dddv dd 101 a a d d v ref dddra3 11x dddd d dddv dd
? 1998-2013 microchip technology inc. ds30605d-page 81 pic16c63a/65b/73b/74b the following steps should be followed for doing an a/d conversion: 1. configure the a/d module: ? configure analog pins, voltage reference, and digital i/o (adcon1) ? select a/d input channel (adcon0) ? select a/d conversion clock (adcon0) ? turn on a/d module (adcon0) 2. configure a/d interrupt (if desired): ? clear adif bit (pir1<6>) ? set adie bit (pie1<6>) ? set peie bit (intcon<6>) ? set gie bit (intcon<7>) 3. wait the required acquisition time. 4. set go/done bit (adcon0) to start conversion. 5. wait for a/d conversion to complete, by either: polling for the go/done bit to be cleared (if interrupts are disabled); or waiting for the a/d interrupt. 6. read a/d result register (adres), clear bit adif if required. 7. for next conversion, go to step 1 or step 2 as required. the a/d conversion time per bit is defined as t ad . a minimum wait of 2 t ad is required before next acquisition starts. figure 12-1: a/d block diagram (input voltage) v in v ref (reference voltage) v dd pcfg2:pcfg0 chs2:chs0 000 or 010 or 100 or 001 or 011 or 101 re2/an7 (1) re1/an6 (1) re0/an5 (1) ra5/an4 ra3/an3/v ref ra2/an2 ra1/an1 ra0/an0 111 110 101 100 011 010 001 000 a/d converter note 1: not available on pic16c73b. 11x
pic16c63a/65b/73b/74b ds30605d-page 82 ? 1998-2013 microchip technology inc. 12.1 a/d acquisition requirements for the a/d converter to meet its specified accuracy, the charge holding capacitor (c hold ) must be allowed to fully charge to the input channel voltage level. the analog input model is shown in figure 12-2. the source impedance (r s ) and the internal sampling switch (r ss ) impedance directly affect the time required to charge the capacitor c hold . the sampling switch (r ss ) impedance varies over the device voltage (v dd ), figure 12-2. the source impedance affects the offset voltage at the analog input (due to pin leakage current). the maximum recommended impedance for ana- log sources is 10 k ? . after the analog input channel is selected (changed), the acquisition time (t acq ) must pass before the conversion can be started. to calculate the minimum acquisition time, equation 12-1 may be used. this equation assumes that 1/2 lsb error is used (512 steps for the a/d). the 1/2 lsb error is the maximum error allowed for the a/d to meet its specified resolution. for more information, see the pic ? mid-range mcu family reference manual (ds33023). in general, how- ever, given a maximum source impedance of 10 k ? and a worst case temperature of 100c, t acq will be no more than 16 ? sec. figure 12-2: analog input model equation 12-1: acquisition time c pin va rs anx 5 pf v dd v t = 0.6 v v t = 0.6 v i leakage r ic 1k sampling switch ss r ss c hold = dac capacitance v ss 6v sampling switch 5v 4v 3v 2v 567891011 (k ? ) v dd = 51.2 pf 500 na legend: c pin v t i leakage r ic ss c hold = input capacitance = threshold voltage = leakage current at the pin due to = interconnect resistance = sampling switch = sample/hold capacitance (from dac) various junctions t acq = = amplifier settling time + hold capacitor charging time + temperature coefficient t amp + t c + t coff t amp = 5 ? s t c = - (51.2 pf)(1 k ? + r ss + r s ) in(1/511) t coff = (temp -25 ? c)(0.05 ? s/ ? c)
? 1998-2013 microchip technology inc. ds30605d-page 83 pic16c63a/65b/73b/74b 12.2 selecting the a/d conversion clock the a/d conversion time per bit is defined as t ad . the a/d conversion requires 9.5 t ad per 8-bit conversion. the source of the a/d conversion clock is software selectable. the four possible options for t ad are: ?2 t osc ?8 t osc ?32 t osc ? internal rc oscillator (2 - 6 ? s) for correct a/d conversions, the a/d conversion clock (t ad ) must be selected to ensure a minimum t ad time (parameter #130). 12.3 configuring analog port pins the adcon1, trisa and trise registers control the operation of the a/d port pins. the port pins that are desired as analog inputs must have their correspond- ing tris bits set (input). if the tris bit is cleared (out- put), the digital output level (v oh or v ol ) will be converted. the a/d operation is independent of the state of the chs2:chs0 bits and the tris bits. 12.4 a/d conversions clearing the go/done bit during a conversion will abort the current conversion. the adres register will not be updated with the partially completed a/d con- version sample. that is, the adres register will con- tinue to contain the value of the last completed conversion (or the last value written to the adres reg- ister). after the a/d conversion is aborted, a 2 t ad wait is required before the next acquisition is started. after this 2 t ad wait, an acquisition is automatically started on the selected channel. the go/done bit can then be set to start another conversion. 12.5 a/d operation during sleep the a/d module can operate during sleep mode. this requires that the a/d clock source be set to rc (adcs1:adcs0 = 11 ). when the rc clock source is selected, the a/d module waits one instruction cycle before starting the conversion. this allows the sleep instruction to be executed, which eliminates all digital switching noise from the conversion. when the conver- sion is completed, the go/done bit will be cleared, and the result loaded into the adres register. if the a/d interrupt is enabled, the device will wake-up from sleep. if the a/d interrupt is not enabled, the a/d mod- ule will then be turned off, although the adon bit will remain set. when the a/d clock source is another clock option (not rc), a sleep instruction will cause the present conver- sion to be aborted and the a/d module to be turned off, though the adon bit will remain set. turning off the a/d places the a/d module in its lowest current consumption state. 12.6 effects of a reset a device reset forces all registers to their reset state. the a/d module is disabled and any conversion in progress is aborted. all pins with analog functions are configured as analog inputs. the adres register will contain unknown data after a power-on reset. 12.7 use of the ccp trigger an a/d conversion can be started by the ?special event trigger? of the ccp2 module. this requires that the ccp2m3:ccp2m0 bits (ccp2con<3:0>) be pro- grammed as 1011 and that the a/d module is enabled (adon bit is set). when the trigger occurs, the go/done bit will be set, starting the a/d conversion, and the timer1 counter will be reset to zero. timer1 is reset to automatically repeat the a/d acquisition period with minimal software overhead (moving the adres to the desired location). the appropriate analog input channel must be selected and the minimum acquisition done before the ?special event trigger? sets the go/done bit (starts a conversion). if the a/d module is not enabled (adon is cleared), then the ?special event trigger? will be ignored by the a/d module, but will still reset the timer1 counter. note 1: when reading the port register, all pins configured as analog input channels will read as cleared (a low level). pins config- ured as digital inputs will convert an ana- log input. analog levels on a digitally configured input will not affect the conver- sion accuracy. 2: analog levels on any pin that is defined as a digital input, but not as an analog input, may cause the input buffer to consume current that is out of the devices specifi- cation. 3: the trise register is not provided on the pic16c73b. note: the go/done bit should not be set in the same instruction that turns on the a/d. note: for the a/d module to operate in sleep, the a/d clock source must be set to rc (adcs1:adcs0 = 11 ). to perform an a/d conversion in sleep, ensure the sleep instruction immediately follows the instruc- tion that sets the go/done bit.
pic16c63a/65b/73b/74b ds30605d-page 84 ? 1998-2013 microchip technology inc. table 12-1: summary of a/d registers (pic16c73b/74b only) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh,8bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 0dh pir2 ? ? ? ? ? ? ? ccp1if ---- ---0 ---- ---0 8dh pie2 ? ? ? ? ? ? ? ccp1ie ---- ---0 ---- ---0 1eh adres a/d result register xxxx xxxx uuuu uuuu 1fh adcon0 adcs1 adcs0 chs2 chs1 chs0 go/done ?adon 0000 00-0 0000 00-0 9fh adcon1 ? ? ? ? ? pcfg2 pcfg1 pcfg0 ---- -000 ---- -000 05h porta ? ? ra5 ra4 ra3 ra2 ra1 ra0 --0x 0000 --0u 0000 85h trisa ? ? porta data direction register --11 1111 --11 1111 09h porte ? ? ? ? ? re2 re1 re0 ---- -xxx ---- -uuu 89h trise ibf obf ibov pspmode ? porte data direction bits 0000 -111 0000 -111 legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. shaded cells are not used for a/d conversion. note 1: bits pspie and pspif are reserved on the pic6c63a/73b; always maintain these bits clear.
? 1998-2013 microchip technology inc. ds30605d-page 85 pic16c63a/65b/73b/74b 13.0 special features of the cpu what sets a microcontroller apart from other proces- sors are special circuits to deal with the needs of real- time applications. the pic16cxx family has a host of such features intended to maximize system reliability, minimize cost through elimination of external compo- nents, provide power saving operating modes and offer code protection. these are: ? oscillator selection ? reset - power-on reset (por) - power-up timer (pwrt) - oscillator start-up timer (ost) - brown-out reset (bor) ? interrupts ? watchdog timer (wdt) ? sleep ? code protection ? id locations ? in-circuit serial programming (icsp) the pic16cxx has a watchdog timer which can be shut off only through configuration bits. it runs off its own rc oscillator for added reliability. there are two timers that offer necessary delays on power-up. one is the oscillator start-up timer (ost), intended to keep the chip in reset until the crystal oscillator is stable. the other is the power-up timer (pwrt), which provides a fixed delay of 72 ms (nominal) on power-up only and is designed to keep the part in reset, while the power supply stabilizes. with these two timers on-chip, most applications need no external reset circuitry. sleep mode is designed to offer a very low current power-down mode. the user can wake-up from sleep through external reset, wdt wake-up or through an interrupt. several oscillator options are also made available to allow the part to fit the application. the rc oscillator option saves system cost, while the lp crystal option saves power. a set of configuration bits are used to select various options. 13.1 configuration bits the configuration bits can be programmed (read as '0') or left unprogrammed (read as '1') to select various device configurations. these bits are mapped in pro- gram memory location 2007h. the user will note that address 2007h is beyond the user program memory space, and can be accessed only during programming. register 13-1: configurat ion word (config 2007h) cp1 cp0 cp1 cp0 cp1 cp0 ? boden cp1 cp0 pwrte wdte fosc1 fosc0 bit 13 bit 0 bits 13-8, 5-4 cp1:cp0 : code protection bits (2) 11 = code protection off 10 = upper half of program memory code protected 01 = upper 3/4th of program memory code protected 00 = all memory is code protected bit 7 unimplemented : read as '1' bit 6 boden : brown-out reset enable bit (1) 1 = bor enabled 0 = bor disabled bit 3 pwrte : power-up timer enable bit (1) 1 = pwrt disabled 0 = pwrt enabled bit 2 wdte : watchdog timer enable bit 1 = wdt enabled 0 = wdt disabled bit 1-0 fosc1:fosc0 : oscillator selection bits 11 = rc oscillator 10 = hs oscillator 01 = xt oscillator 00 = lp oscillator note 1: enabling brown-out reset automatically enables power-up timer (pwrt), regardless of the value of pwrte . 2: all of the cp1:cp0 pairs have to be given the same value to enable the code protection scheme listed.
pic16c63a/65b/73b/74b ds30605d-page 86 ? 1998-2013 microchip technology inc. 13.2 oscillator configurations 13.2.1 oscillator types the pic16cxx can be operated in four different oscil- lator modes. the user can program two configuration bits (fosc1 and fosc0) to select one of these four modes: ? lp low power crystal ? xt crystal/resonator ? hs high speed crystal/resonator ? rc resistor/capacitor 13.2.2 crystal oscillator/ceramic resonators in xt, lp, or hs modes, a crystal or ceramic resonator is connected to the osc1/clkin and osc2/clkout pins to establish oscillation (figure 13-1). the pic16cxx oscillator design requires the use of a par- allel cut crystal. use of a series cut crystal may give a frequency out of the crystal manufacturers specifica- tions. when in xt, lp or hs modes, the device can have an external clock source to drive the osc1/ clkin pin (figure 13-2). see the pic ? mid-range mcu reference manual (ds33023) for details on building an external oscillator. figure 13-1: crystal/ceramic resonator operation (hs, xt or lp osc configuration) figure 13-2: external clock input operation (hs, xt or lp osc configuration) c1 c2 xtal osc2 (note 1) osc1 r f sleep to internal logic pic16cxx rs see table 13-1 and table 13-2 for recommended values of c1 and c2. note 1: a series resistor may be required for at strip cut crystals. osc1 osc2 open clock from ext. system pic16cxx
? 1998-2013 microchip technology inc. ds30605d-page 87 pic16c63a/65b/73b/74b table 13-1: ceramic resonators table 13-2: capacitor selection for crystal oscillator 13.2.3 rc oscillator for timing insensitive applications, the ?rc? device option offers additional cost savings. the rc oscillator frequency is a function of the supply voltage, the resis- tor (r ext ) and capacitor (c ext ) values, and the operat- ing temperature. the oscillator frequency will vary from unit to unit due to normal process variation. the differ- ence in lead frame capacitance between package types will also affect the oscillation frequency, espe- cially for low c ext values. the user also needs to take into account variation due to tolerance of external r and c components used. figure 13-3 shows how the r/c combination is connected to the pic16cxx. the oscillator frequency, divided by 4, is available on the osc2/clkout pin, and can be used for test pur- poses or to synchronize other logic (see figure 3-2 for waveform). figure 13-3: rc oscillator mode ranges tested: mode freq osc1 osc2 xt 455 khz 2.0 mhz 4.0 mhz 68 - 100 pf 15 - 68 pf 15 - 68 pf 68 - 100 pf 15 - 68 pf 15 - 68 pf hs 8.0 mhz 16.0 mhz 10 - 68 pf 10 - 22 pf 10 - 68 pf 10 - 22 pf note: these values are for design guidance only. see notes following table 13-1 and table 13-2. resonators used: 455 khz panasonic efo-a455k04b 0.3% 2.0 mhz murata erie csa2.00mg 0.5% 4.0 mhz murata erie csa4.00mg 0.5% 8.0 mhz murata erie csa8.00mt 0.5% 16.0 mhz murata erie csa16.00mx 0.5% note: resonators used did not have built-in capacitors. osc type crystal freq cap. range c1 cap. range c2 lp 32 khz 33 pf 33 pf 200 khz 15 pf 15 pf xt 200 khz 47-68 pf 47-68 pf 1 mhz 15 pf 15 pf 4 mhz 15 pf 15 pf hs 4 mhz 15 pf 15 pf 8 mhz 15-33 pf 15-33 pf 20 mhz 15-33 pf 15-33 pf note: these values are for design guidance only. see notes following table 13-1 and table 13-2. crystals used: 32 khz epson c-001r32.768k-a 20 ppm 200 khz std xtl 200.000khz 20 ppm 1 mhz ecs ecs-10-13-1 50 ppm 4 mhz ecs ecs-40-20-1 50 ppm 8 mhz epson ca-301 8.000m-c 30 ppm 20 mhz epson ca-301 20.000m-c 30 ppm note 1: higher capacitance increases the stability of the oscillator, but also increases the start-up time. 2: since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external compo- nents. 3: rs may be required in hs mode, as well as xt mode, to avoid overdriving crystals with low drive level specification. 4: oscillator performance should be verified at the expected voltage and temperature extremes in which the application is expected to operate. osc2/clkout c ext v dd r ext v ss pic16cxx osc1 f osc /4 internal clock recommended values: r ext = 3 kw to 100 kw c ext = 20 pf to 30 pf
pic16c63a/65b/73b/74b ds30605d-page 88 ? 1998-2013 microchip technology inc. 13.3 reset the pic16cxx differentiates between various kinds of reset: ? power-on reset (por) ?mclr reset during normal operation ?mclr reset during sleep ? wdt reset (normal operation) ? brown-out reset (bor) some registers are not affected in any reset condi- tion; their status is unknown on por and unchanged in any other reset. most other registers are reset to a ?reset state? on por, on the mclr and wdt reset, on mclr reset during sleep, and on bor. the to and pd bits are set or cleared differently in different reset situations, as indicated in table 13-4. these bits are used in software to determine the nature of the reset. see table 13-6 for a full description of reset states of all registers. a simplified block diagram of the on-chip reset circuit is shown in figure 13-4. the pic devices have a mclr noise filter in the mclr reset path. the filter will detect and ignore small pulses. it should be noted that internal reset sources do not drive mclr pin low. figure 13-4: simplified block di agram of on-chip reset circuit s r q external reset mclr v dd osc1 wdt module v dd rise detect ost/pwrt on-chip rc osc wdt time-out power-on reset ost 10-bit ripple counter pwrt chip reset 10-bit ripple counter reset enable ost enable pwrt sleep note 1: this is a separate oscillator from the rc oscillator of the clkin pin. brown-out reset boden (note 1)
? 1998-2013 microchip technology inc. ds30605d-page 89 pic16c63a/65b/73b/74b 13.4 resets 13.4.1 power-on reset (por) a power-on reset pulse is generated on-chip when v dd rise is detected (parameters d003 and d004, in the range of 1.5v - 2.1v). to take advantage of the por, just tie the mclr pin directly (or through a resis- tor) to v dd . this will eliminate external rc components usually needed to create a por. when the device starts normal operation (exits the reset condition), device operating parameters (volt- age, frequency, temperature) must be met to ensure operation. if these conditions are not met, the device must be held in reset until the operating conditions are met. the device may be held in reset by keeping mclr at vss. for additional information, refer to application note an607, ? power-up trouble shooting .? 13.4.2 power-up timer (pwrt) the power-up timer provides a fixed 72 ms nominal time-out on power-up from the por. the pwrt oper- ates on an internal rc oscillator. the device is kept in reset as long as the pwrt is active. the pwrt?s time delay allows v dd to rise to an acceptable level. a configuration bit is provided to enable/disable the pwrt. the power-up time delay will vary from chip to chip, due to v dd , temperature and process variation. see dc parameters for details (t pwrt , parameter #33). 13.4.3 oscillator start-up timer (ost) the oscillator start-up timer provides a delay of 1024 oscillator cycles (from osc1 input) after the pwrt delay, if enabled. this helps to ensure that the crystal oscillator or resonator has started and stabilized. the ost time-out is invoked only for xt, lp and hs modes and only on power-on reset or wake-up from sleep. 13.4.4 brown-out reset (bor) the configuration bit, boden, can enable or disable the brown-out reset circuit. if v dd falls below v bor (parameter d005, about 4v) for longer than t bor (parameter #35, about 100 ? s), the brown-out situation will reset the device. if v dd falls below v bor for less than t bor , a reset may not occur. once the brown-out occurs, the device will remain in brown-out reset until v dd rises above v bor . the power-up timer then keeps the device in reset for t pwrt (parameter #33, about 72ms). if v dd should fall below v bor during t pwrt , the brown-out reset pro- cess will restart when v dd rises above v bor with the power-up timer reset. the power-up timer is always enabled when the brown-out reset circuit is enabled, regardless of the state of the pwrt configuration bit. 13.4.5 time-out sequence on power-up, the time-out sequence is as follows: the pwrt delay starts (if enabled) when a por occurs. then, ost starts counting 1024 oscillator cycles when pwrt ends (lp, xt, hs). when the ost ends, the device comes out of reset. if mclr is kept low long enough, the time-outs will expire. bringing mclr high will begin execution imme- diately. this is useful for testing purposes or to synchro- nize more than one pic16cxx device operating in parallel. table 13-5 shows the reset conditions for the status, pcon and pc registers, while table 13-6 shows the reset conditions for all the registers. 13.4.6 power control/status register (pcon) the brown-out reset status bit, bor , is unknown on a por. it must be set by the user and checked on sub- sequent resets to see if bit bor was cleared, indi- cating a bor occurred. the bor bit is not predictable if the brown-out reset circuitry is disabled. the power-on reset status bit, por , is cleared on a por and unaffected otherwise. the user must set this bit following a por and check it on subsequent resets to see if it has been cleared.
pic16c63a/65b/73b/74b ds30605d-page 90 ? 1998-2013 microchip technology inc. table 13-3: time-out in various situations table 13-4: status bits and their significance legend: x = don?t care, u = unchanged table 13-5: reset condition for special registers register 13-2: status register register 13-3: pcon register oscillator configuration power-up brown-out wake-up from sleep pwrte = 0 pwrte = 1 xt, hs, lp 72 ms + 1024t osc 1024t osc 72 ms + 1024t osc 1024t osc rc 72 ms ? 72 ms ? por bor to pd 0x11 power-on reset 0x0x illegal, to is set on por 0xx0 illegal, pd is set on por 1011 brown-out reset 1101 wdt reset 1100 wdt wake-up 11uu mclr reset during normal operation 1110 mclr reset during sleep or interrupt wake-up from sleep condition program counter status register pcon register power-on reset 000h 0001 1xxx ---- --0x mclr reset during normal operation 000h 000u uuuu ---- --uu mclr reset during sleep 000h 0001 0uuu ---- --uu wdt reset 000h 0000 1uuu ---- --uu wdt wake-up pc + 1 uuu0 0uuu ---- --uu brown-out reset 000h 000x xuuu ---- --u0 interrupt wake-up from sleep pc + 1 (1) uuu1 0uuu ---- --uu legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0' note 1: when the wake-up is due to an interrupt and the gie bit is set, the pc is loaded with the interrupt vector (0004h). irp rp1 rp0 to pd z dc c ? ? ? ? ? ?por bor
? 1998-2013 microchip technology inc. ds30605d-page 91 pic16c63a/65b/73b/74b table 13-6: initialization conditions for all registers register applicable devices power-on reset brown-out reset mclr resets wdt reset wake-up via wdt or interrupt w 63a 65b 73b 74b xxxx xxxx uuuu uuuu uuuu uuuu indf 63a 65b 73b 74b n/a n/a n/a tmr0 63a 65b 73b 74b xxxx xxxx uuuu uuuu uuuu uuuu pcl 63a 65b 73b 74b 0000h 0000h pc + 1 (2) status 63a 65b 73b 74b 0001 1xxx 000q quuu (3) uuuq quuu (3) fsr 63a 65b 73b 74b xxxx xxxx uuuu uuuu uuuu uuuu porta 63a 65b 73b 74b --0x 0000 --0u 0000 --uu uuuu portb 63a 65b 73b 74b xxxx xxxx uuuu uuuu uuuu uuuu portc 63a 65b 73b 74b xxxx xxxx uuuu uuuu uuuu uuuu portd 63a 65b 73b 74b xxxx xxxx uuuu uuuu uuuu uuuu porte 63a 65b 73b 74b ---- -xxx ---- -uuu ---- -uuu pclath 63a 65b 73b 74b ---0 0000 ---0 0000 ---u uuuu intcon 63a 65b 73b 74b 0000 000x 0000 000u uuuu uuuu (1) pir1 63a 65b 73b 74b -0-- 0000 -0-- 0000 -u-- uuuu (1) 63a 65b 73b 74b -000 0000 -000 0000 -uuu uuuu (1) 63a 65b 73b 74b 0000 0000 0000 0000 uuuu uuuu (1) 63a 65b 73b 74b 0000 0000 0000 0000 uuuu uuuu (1) pir2 63a 65b 73b 74b ---- ---0 ---- ---0 ---- ---u (1) tmr1l 63a 65b 73b 74b xxxx xxxx uuuu uuuu uuuu uuuu tmr1h 63a 65b 73b 74b xxxx xxxx uuuu uuuu uuuu uuuu t1con 63a 65b 73b 74b --00 0000 --uu uuuu --uu uuuu tmr2 63a 65b 73b 74b 0000 0000 0000 0000 uuuu uuuu t2con 63a 65b 73b 74b -000 0000 -000 0000 -uuu uuuu sspbuf 63a 65b 73b 74b xxxx xxxx uuuu uuuu uuuu uuuu sspcon 63a 65b 73b 74b 0000 0000 0000 0000 uuuu uuuu ccpr1l 63a 65b 73b 74b xxxx xxxx uuuu uuuu uuuu uuuu ccpr1h 63a 65b 73b 74b xxxx xxxx uuuu uuuu uuuu uuuu ccp1con 63a 65b 73b 74b --00 0000 --00 0000 --uu uuuu rcsta 63a 65b 73b 74b 0000 -00x 0000 -00x uuuu -uuu txreg 63a 65b 73b 74b 0000 0000 0000 0000 uuuu uuuu rcreg 63a 65b 73b 74b 0000 0000 0000 0000 uuuu uuuu ccpr2l 63a 65b 73b 74b xxxx xxxx uuuu uuuu uuuu uuuu ccpr2h 63a 65b 73b 74b xxxx xxxx uuuu uuuu uuuu uuuu ccp2con 63a 65b 73b 74b 0000 0000 0000 0000 uuuu uuuu adres 63a 65b 73b 74b xxxx xxxx uuuu uuuu uuuu uuuu legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition note 1: one or more bits in intcon, pir1 and/or pir2 will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the gie bit is set, the pc is loaded with the interrupt vector (0004h). 3: see table 13-5 for reset value for specific condition.
pic16c63a/65b/73b/74b ds30605d-page 92 ? 1998-2013 microchip technology inc. adcon0 63a 65b 73b 74b 0000 00-0 0000 00-0 uuuu uu-u option_reg 63a 65b 73b 74b 1111 1111 1111 1111 uuuu uuuu trisa 63a 65b 73b 74b --11 1111 --11 1111 --uu uuuu trisb 63a 65b 73b 74b 1111 1111 1111 1111 uuuu uuuu trisc 63a 65b 73b 74b 1111 1111 1111 1111 uuuu uuuu trisd 63a 65b 73b 74b 1111 1111 1111 1111 uuuu uuuu trise 63a 65b 73b 74b 0000 -111 0000 -111 uuuu -uuu pie1 63a 65b 73b 74b --00 0000 --00 0000 --uu uuuu 63a 65b 73b 74b 0-00 0000 0-00 0000 u-uu uuuu 63a 65b 73b 74b -000 0000 -000 0000 -uuu uuuu 63a 65b 73b 74b 0000 0000 0000 0000 uuuu uuuu pie2 63a 65b 73b 74b ---- ---0 ---- ---0 ---- ---u pcon 63a 65b 73b 74b ---- --0q (3) ---- --uu ---- --uu pr2 63a 65b 73b 74b 1111 1111 1111 1111 1111 1111 sspadd 63a 65b 73b 74b 0000 0000 0000 0000 uuuu uuuu sspstat 63a 65b 73b 74b --00 0000 --00 0000 --uu uuuu txsta 63a 65b 73b 74b 0000 -010 0000 -010 uuuu -uuu spbrg 63a 65b 73b 74b 0000 0000 0000 0000 uuuu uuuu adcon1 63a 65b 73b 74b ---- -000 ---- -000 ---- -uuu table 13-6: initialization conditions for all registers (continued) register applicable devices power-on reset brown-out reset mclr resets wdt reset wake-up via wdt or interrupt legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition note 1: one or more bits in intcon, pir1 and/or pir2 will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the gie bit is set, the pc is loaded with the interrupt vector (0004h). 3: see table 13-5 for reset value for specific condition.
? 1998-2013 microchip technology inc. ds30605d-page 93 pic16c63a/65b/73b/74b 13.5 interrupts the interrupt control register (intcon) records indi- vidual interrupt requests in flag bits. it also has individ- ual and global interrupt enable bits. a global interrupt enable bit, gie (intcon<7>), enables (if set) all unmasked interrupts, or disables (if cleared) all interrupts. when bit gie is enabled, and an interrupt?s flag bit and mask bit are set, the interrupt will vector immediately. individual interrupts can be dis- abled through their corresponding enable bits in vari- ous registers. individual interrupt bits are set, regardless of the status of the gie bit. the gie bit is cleared on reset. the ?return from interrupt? instruction, retfie , exits the interrupt routine, as well as sets the gie bit, which re-enables interrupts. the rb0/int pin interrupt, the rb port change interrupt and the tmr0 overflow interrupt flags are contained in the intcon register. the peripheral interrupt flags are contained in the spe- cial function registers pir1 and pir2. the correspond- ing interrupt enable bits are contained in special function registers pie1 and pie2 and the peripheral interrupt enable bit is contained in special function reg- ister intcon. when an interrupt is responded to, the gie bit is cleared to disable any further interrupt, the return address is pushed onto the stack, and the pc is loaded with 0004h. once in the interrupt service routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. the interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid recursive interrupts. for external interrupt events, such as the int pin or portb change interrupt, the interrupt latency will be three or four instruction cycles. the exact latency depends when the interrupt event occurs. the latency is the same for one or two cycle instructions. individual interrupt flag bits are set, regardless of the status of their corresponding mask bit, peie bit, or the gie bit. note: individual interrupt flag bits are set, regard- less of the status of their corresponding mask bit, or the gie bit. note: if an interrupt occurs while the global inter- rupt enable (gie) bit is being cleared, the gie bit may unintentionally be re-enabled by the user?s interrupt service routine (the retfie instruction). the events that would cause this to occur are: 1. an instruction clears the gie bit while an interrupt is acknowledged. 2. the program branches to the interrupt vector and executes the interrupt service routine. 3. the interrupt service routine completes the execution of the retfie instruction. this causes the gie bit to be set (enables interrupts), and the program returns to the instruction after the one which was meant to disable interrupts. perform the following to ensure that inter- rupts are globally disabled: loop bcf intcon, gie ; disable global ; interrupt bit btfsc intcon, gie ; global interrupt ; disabled? goto loop ; no, try again : ; yes, continue ; with program ; flow
pic16c63a/65b/73b/74b ds30605d-page 94 ? 1998-2013 microchip technology inc. figure 13-5: interrupt logic 13.5.1 int interrupt the external interrupt on rb0/int pin is edge trig- gered: either rising if bit intedg (option_reg<6>) is set, or falling if the intedg bit is clear. when a valid edge appears on the rb0/int pin, flag bit intf (intcon<1>) is set. this interrupt can be disabled by clearing enable bit inte (intcon<4>). flag bit intf must be cleared in software in the interrupt service routine before re-enabling this interrupt. the int inter- rupt can wake-up the processor from sleep, if bit inte was set prior to going into sleep. the status of global interrupt enable bit gie decides whether or not the pro- cessor branches to the interrupt vector following wake- up. see section 13.8 for details on sleep mode. 13.5.2 tmr0 interrupt an overflow (ffh ? 00h) in the tmr0 register will set flag bit t0if (intcon<2>). the interrupt can be enabled/disabled by setting/clearing enable bit t0ie (intcon<5>) (see section 6.0). 13.5.3 portb interrupt-on-change an input change on portb<7:4> sets flag bit rbif (intcon<0>). the interrupt can be enabled/disabled by setting/clearing enable bit rbie (intcon<4>). (section 5.2) pspif pspie adif adie rcif rcie txif txie sspif sspie ccp1if ccp1ie tmr2if tmr2ie tmr1if tmr1ie t0if t0ie intf inte rbif rbie gie peie wake-up (if in sleep mode) interrupt to cpu ccp2ie ccp2if the following table shows which devices have which interrupts. device t0if intf rbif pspif adif rcif txif sspif ccp1if tmr2if tmr1if ccp2if pic16c63a yes yes yes ? ? yes yes yes yes yes yes yes pic16c65b yes yes yes yes ? yes yes yes yes yes yes yes pic16c73b yes yes yes ? yes yes yes yes yes yes yes yes pic16c74b yes yes yes yes yes yes yes yes yes yes yes yes note: if a change on the i/o pin should occur when the read operation is being executed (start of the q2 cycle), then the rbif inter- rupt flag may not get set.
? 1998-2013 microchip technology inc. ds30605d-page 95 pic16c63a/65b/73b/74b 13.6 context saving during interrupts during an interrupt, only the return pc value is saved on the stack. users may wish to save key registers dur- ing an interrupt i.e., w register and status register. this will have to be implemented in software. example 13-1 stores and restores the status, w, and pclath registers. the register w_temp must be defined in each bank and must be defined at the same offset from the bank base address (i.e., if w_temp is defined at 0x20 in bank 0, it must also be defined at 0xa0 in bank 1). the example: a) stores the w register. b) stores the status register in bank 0. c) stores the pclath register. d) executes the isr code. e) restores the status register (and bank select bit). f) restores the w and pclath registers. example 13-1: saving status, w, and pclath registers in ram movwf w_temp ;copy w to temp register, could be bank one or zero swapf status,w ;swap status to be saved into w clrf status ;bank 0, regardless of current bank, clears irp,rp1,rp0 movwf status_temp ;save status to bank zero status_temp register movf pclath, w ;only required if using pages 1, 2 and/or 3 movwf pclath_temp ;save pclath into w : (isr) ;user isr code goes here : movf pclath_temp, w ;restore pclath movwf pclath ;move w into pclath swapf status_temp, w ;swap status_temp register into w ;(sets bank to original state) movwf status ;move w into status register swapf w_temp,f ;swap w_temp swapf w_temp,w ;swap w_temp into w 13.7 watchdog timer (wdt) the watchdog timer is a free running on-chip rc oscil- lator, which does not require any external components. this rc oscillator is separate from the rc oscillator of the osc1/clkin pin. the wdt will run, even if the clock on the osc1/clkin and osc2/clkout pins of the device has been stopped, for example, by execu- tion of a sleep instruction. during normal operation, a wdt time-out generates a device reset (watchdog timer reset). if the device is in sleep mode, a wdt time-out causes the device to wake-up and resume normal operation (watchdog timer wake-up). the wdt can be permanently disabled by clearing configuration bit wdte (section 13.1). 13.7.1 wdt period the wdt has a nominal time-out period of 18 ms (parameter #31, t wdt ). the time-out periods vary with temperature, v dd , and process variations. if longer time-out periods are desired, a prescaler with a division ratio of up to 1:128 can be assigned to the wdt under software control, by writing to the option register. time-out periods up to 128 t wdt can be realized. the clrwdt and sleep instructions clear the wdt and the postscaler, if assigned to the wdt. in addition, the sleep instruction prevents the wdt from generat- ing a reset, but will allow the wdt to wake the device from sleep mode. the to bit in the status register will be cleared upon a wdt time-out.
pic16c63a/65b/73b/74b ds30605d-page 96 ? 1998-2013 microchip technology inc. 13.7.2 wdt programming considerations it should also be taken into account that under worst case conditions (v dd = min., temperature = max., and max. wdt prescaler), it may take several seconds before a wdt time-out occurs. figure 13-6: watchdog timer block diagram table 13-7: summary of watchdog timer registers note: when a clrwdt instruction is executed and the prescaler is assigned to the wdt, the prescaler count will be cleared, but the prescaler assignment is not changed. from tmr0 clock source (figure 6-1) to tmr0 mux (figure 6-1) postscaler wdt timer wdt enable bit 0 1 m u x psa 8 - to - 1 mux ps2:ps0 0 1 mux psa wdt time-out note: psa and ps2:ps0 are bits in the option register. 8 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2007h config. bits ? boden (1) cp1 cp0 pwrte (1) wdte fosc1 fosc0 81h option_reg rbpu intedg t0cs t0se psa ps2 ps1 ps0 legend: shaded cells are not used by the watchdog timer. note 1: see register 13-1 for operation of these bits.
? 1998-2013 microchip technology inc. ds30605d-page 97 pic16c63a/65b/73b/74b 13.8 power-down mode (sleep) power-down mode is entered by executing a sleep instruction. if enabled, the wdt will be cleared but keeps running, the pd bit (status<3>) is cleared, the to (sta- tus<4>) bit is set, and the oscillator driver is turned off. the i/o ports maintain the status they had, before the sleep instruction was executed (driving high, low, or hi-impedance). for lowest current consumption in this mode, place all i/o pins at either v dd or v ss , ensure no external cir- cuitry is drawing current from the i/o pin, power-down the a/d, and disable external clocks. pull all i/o pins that are hi-impedance inputs, high or low externally, to avoid switching currents caused by floating inputs. the t0cki input should also be at v dd or v ss for lowest current consumption. the contribution from on-chip pull-ups on portb should also be considered. the mclr pin must be at a logic high level (v ihmc ). 13.8.1 wake-up from sleep the device can wake up from sleep through one of the following events: 1. external reset input on mclr pin. 2. watchdog timer wake-up (if wdt was enabled). 3. interrupt from int pin, rb port change or a peripheral interrupt. external mclr reset will cause a device reset. all other events are considered a continuation of program execution and cause a ?wake-up?. the to and pd bits in the status register can be used to determine the cause of device reset. the pd bit, which is set on power-up, is cleared when sleep is invoked. the to bit is cleared if a wdt time-out occurred (and caused wake-up). the following peripheral interrupts can wake the device from sleep: 1. tmr1 interrupt. timer1 must be operating as an asynchronous counter. 2. ssp (start/stop) bit detect interrupt. 3. ssp transmit or receive in slave mode (spi/i 2 c). 4. ccp capture mode interrupt. 5. parallel slave port read or write (pic16c65b/74b only). 6. a/d conversion (when a/d clock source is rc). 7. usart tx or rx (synchronous slave mode). other peripherals cannot generate interrupts since dur- ing sleep, no on-chip q clocks are present. when the sleep instruction is being executed, the next instruction (pc + 1) is pre-fetched. for the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). wake-up is regardless of the state of the gie bit. if the gie bit is clear (disabled), the device continues execution at the instruction after the sleep instruction. if the gie bit is set (enabled), the device executes the instruction after the sleep instruction and then branches to the inter- rupt address (0004h). in cases where the execution of the instruction following sleep is not desirable, the user should have a nop after the sleep instruction. 13.8.2 wake-up using interrupts when global interrupts are disabled (gie cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: ? if the interrupt occurs before the execution of a sleep instruction, the sleep instruction will com- plete as a nop . therefore, the wdt and wdt postscaler will not be cleared, the to bit will not be set and pd bit will not be cleared. ? if the interrupt occurs during or after the execu- tion of a sleep instruction, the device will imme- diately wake up from sleep. the sleep instruction will be completely executed before the wake-up. therefore, the wdt and wdt postscaler will be cleared, the to bit will be set and the pd bit will be cleared. even if the flag bits were checked before executing a sleep instruction, it may be possible for flag bits to become set before the sleep instruction completes. to determine whether a sleep instruction executed, test the pd bit. if the pd bit is set, the sleep instruction was executed as a nop . to ensure that the wdt is cleared, a clrwdt instruc- tion should be executed before a sleep instruction.
pic16c63a/65b/73b/74b ds30605d-page 98 ? 1998-2013 microchip technology inc. figure 13-7: wake-up from sleep through interrupt 13.9 program verification/code protection if the code protection bit(s) have not been pro- grammed, the on-chip program memory can be read out for verification purposes. 13.10 id locations four memory locations (2000h - 2003h) are designated as id locations where the user can store checksum or other code identification numbers. these locations are not accessible during normal execution, but are read- able and writable during program/verify. it is recom- mended that only the four least significant bits of the id location are used. 13.11 in-circuit serial programming pic16cxx microcontrollers can be serially pro- grammed while in the end application circuit. this is simply done with two lines for clock and data, and three other lines for power, ground and the programming voltage. this allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. this also allows the most recent firmware or a custom firm- ware to be programmed. the device is placed into a program/verify mode by holding the rb6 and rb7 pins low, while raising the mclr (v pp ) pin from v il to v ihh (see programming specification). rb6 becomes the programming clock and rb7 becomes the programming data. both rb6 and rb7 are schmitt trigger inputs in this mode. after reset, to place the device into programming/ verify mode, the program counter (pc) is at location 00h. a 6-bit command is then supplied to the device. depending on the command, 14 bits of program data are then supplied to or from the device, depending if the command was a load or a read. for complete details of serial programming, please refer to the pic16c6x/7x programming specifications (literature #ds30228). figure 13-8: typical in-circuit serial programming connection q1 q2 q3 q4 q1 q2 q3 q4 q1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 clkout (4) int pin intf flag (intcon<1>) gie bit (intcon<7>) instruction flow pc instruction fetched instruction executed pc pc+1 pc+2 inst(pc) = sleep inst(pc - 1) inst(pc + 1) sleep processor in sleep interrupt latency (2) inst(pc + 2) inst(pc + 1) inst(0004h) inst(0005h) inst(0004h) dummy cycle pc + 2 0004h 0005h dummy cycle t ost (2) pc+2 note 1: xt, hs or lp oscillator mode assumed. 2: t ost = 1024tosc (drawing not to scale). this delay is not present in rc osc mode. 3: gie = '1' assumed. after wake- up, the processor jumps to the in terrupt routine. if gie = '0', execution will continue in-line. 4: clkout is not available in these osc modes, but shown here for timing reference. note: microchip does not recommend code pro- tecting windowed devices. devices that are code protected may be erased, but not programmed again. external connector signals to n o rm a l connections to n o rm a l connections pic16cxx v dd v ss mclr /v pp rb6 rb7 +5v 0v v pp clk data i/o v dd
? 1998-2013 microchip technology inc. ds30605d-page 99 pic16c63a/65b/73b/74b 14.0 instruction set summary each pic16cxx instruction is a 14-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. the pic16cxx instruction set summary in table 14-2 lists byte-oriented , bit-ori- ented , and literal and control operations. table 14-1 shows the opcode field descriptions. for byte-oriented instructions, 'f' represents a file reg- ister designator and 'd' represents a destination desig- nator. the file register designator specifies which file register is to be used by the instruction. the destination designator specifies where the result of the operation is to be placed. if 'd' is zero, the result is placed in the w register. if 'd' is one, the result is placed in the file register specified in the instruction. for bit-oriented instructions, 'b' represents a bit field designator which selects the number of the bit affected by the operation, while 'f' represents the address of the file in which the bit is located. for literal and control operations, 'k' represents an eight or eleven bit constant or literal value. table 14-1: opcode field descriptions the instruction set is highly orthogonal and is grouped into three basic categories: ? byte-oriented operations ? bit-oriented operations ? literal and control operations all instructions are executed within one single instruc- tion cycle, unless a conditional test is true or the pro- gram counter is changed as a result of an instruction. in this case, the execution takes two instruction cycles with the second cycle executed as a nop . one instruc- tion cycle consists of four oscillator periods. thus, for an oscillator frequency of 4 mhz, the normal instruction execution time is 1 ? s. if a conditional test is true or the program counter is changed as a result of an instruc- tion, the instruction execution time is 2 ? s. table 14-2 lists the instructions recognized by the mpasm tm assembler. figure 14-1 shows the general formats that the instruc- tions can have. all examples use the following format to represent a hexadecimal number: 0xhh where h signifies a hexadecimal digit. figure 14-1: general format for instructions field description f register file address (0x00 to 0x7f) w working register (accumulator) b bit address within an 8-bit file register k literal field, constant data or label x don't care location (= 0 or 1) the assembler will generate code with x = 0. it is the recommended form of use for compatibility with all microchip software tools. d destination select; d = 0: store result in w, d = 1: store result in file register f. default is d = 1 label label name tos top-of-stack pc program counter pclath program counter high latch gie global interrupt enable bit wdt watchdog timer/counter to time-out bit pd power-down bit dest destination either the w register or the specified register file location [ ] options ( ) contents ? assigned to < > register bit field ? in the set of i talics user defined term (font is courier) note: to maintain upward compatibility with future pic16cxx products, do not use the option and tris instructions. byte-oriented file register operations 13 8 7 6 0 d = 0 for destination w opcode d f (file #) d = 1 for destination f f = 7-bit file register address bit-oriented file register operations 13 10 9 7 6 0 opcode b (bit #) f (file #) b = 3-bit bit address f = 7-bit file register address literal and control operations 13 8 7 0 opcode k (literal) k = 8-bit immediate value 13 11 10 0 opcode k (literal) k = 11-bit immediate value general call and goto instructions only
pic16c63a/65b/73b/74b ds30605d-page 100 ? 1998-2013 microchip technology inc. table 14-2: pic16cxx instruction set mnemonic, operands description cycles 14-bit opcode status affected notes msb lsb byte-oriented file register operations addwf andwf clrf clrw comf decf decfsz incf incfsz iorwf movf movwf nop rlf rrf subwf swapf xorwf f, d f, d f - f, d f, d f, d f, d f, d f, d f, d f - f, d f, d f, d f, d f, d add w and f and w with f clear f clear w complement f decrement f decrement f, skip if 0 increment f increment f, skip if 0 inclusive or w with f move f move w to f no operation rotate left f through carry rotate right f through carry subtract w from f swap nibbles in f exclusive or w with f 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 dfff dfff lfff 0000 dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff ffff ffff ffff 0011 ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff c,dc,z z z z z z z z z c c c,dc,z z 1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2 1,2 1,2 1,2 1,2 1,2 bit-oriented file register operations bcf bsf btfsc btfss f, b f, b f, b f, b bit clear f bit set f bit test f, skip if clear bit test f, skip if set 1 1 1 (2) 1 (2) 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff 1,2 1,2 3 3 literal and control operations addlw andlw call clrwdt goto iorlw movlw retfie retlw return sleep sublw xorlw k k k - k k k - k - - k k add literal and w and literal with w call subroutine clear watchdog timer go to address inclusive or literal with w move literal to w return from interrupt return with literal in w return from subroutine go into standby mode subtract w from literal exclusive or literal with w 1 1 2 1 2 1 1 2 2 2 1 1 1 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk c,dc,z z to , pd z to , pd c,dc,z z note 1: when an i/o register is modified as a function of itself ( e.g., movf portb, 1), the value used will be that value present on the pins themselves. for example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 2: if this instruction is executed on the tmr0 register ( and, where applicable, d = 1), the prescaler will be cleared if assigned to the timer0 module. 3: if program counter (pc) is modified or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop . note: additional information on the mid-range instruction set is available in the picmicro tm mid-range mcu family reference manual (ds33023).
? 1998-2013 microchip technology inc. ds30605d-page 101 pic16c63a/65b/73b/74b 14.1 instruction descriptions addlw add literal and w syntax: [ label ] addlw k operands: 0 ? k ? 255 operation: (w) + k ? (w) status affected: c, dc, z description: the contents of the w register are added to the eight bit literal 'k' and the result is placed in the w register. addwf add w and f syntax: [ label ] addwf f,d operands: 0 ? f ? 127 d ??????? operation: (w) + (f) ? (destination) status affected: c, dc, z description: add the contents of the w register with register 'f'. if 'd' is 0, the result is stored in the w register. if 'd' is 1, the result is stored back in register 'f'. andlw and literal with w syntax: [ label ] andlw k operands: 0 ? k ? 255 operation: (w) .and. (k) ? (w) status affected: z description: the contents of w register are and?ed with the eight bit literal 'k'. the result is placed in the w register. andwf and w with f syntax: [ label ] andwf f,d operands: 0 ? f ? 127 d ??????? operation: (w) .and. (f) ? (destination) status affected: z description: and the w register with register 'f'. if 'd' is 0, the result is stored in the w register. if 'd' is 1, the result is stored back in register 'f'. bcf bit clear f syntax: [ label ] bcf f,b operands: 0 ? f ? 127 0 ? b ? 7 operation: 0 ? (f) status affected: none description: bit 'b' in register 'f' is cleared. bsf bit set f syntax: [ label ] bsf f,b operands: 0 ? f ? 127 0 ? b ? 7 operation: 1 ? (f) status affected: none description: bit 'b' in register 'f' is set.
pic16c63a/65b/73b/74b ds30605d-page 102 ? 1998-2013 microchip technology inc. btfss bit test f, skip if set syntax: [ label ] btfss f,b operands: 0 ? f ? 127 0 ? b < 7 operation: skip if (f) = 1 status affected: none description: if bit 'b' in register 'f' is '0', the next instruction is executed. if bit 'b' is '1', then the next instruction is discarded and a nop is executed instead making this a 2t cy instruction. btfsc bit test, skip if clear syntax: [ label ] btfsc f,b operands: 0 ? f ? 127 0 ? b ? 7 operation: skip if (f) = 0 status affected: none description: if bit 'b' in register 'f' is '1', the next instruction is executed. if bit 'b', in register 'f', is '0', the next instruction is discarded, and a nop is executed instead, making this a 2 t cy instruction. call call subroutine syntax: [ label ] call k operands: 0 ? k ? 2047 operation: (pc)+ 1 ? tos, k ? pc<10:0>, (pclath<4:3>) ? pc<12:11> status affected: none description: call subroutine. first, return address (pc+1) is pushed onto the stack. the eleven bit immediate address is loaded into pc bits <10:0>. the upper bits of the pc are loaded from pclath. call is a two-cycle instruction. clrf clear f syntax: [ label ] clrf f operands: 0 ? f ? 127 operation: 00h ? (f) 1 ? z status affected: z description: the contents of register 'f' are cleared and the z bit is set. clrw clear w syntax: [ label ] clrw operands: none operation: 00h ? (w) 1 ? z status affected: z description: w register is cleared. zero bit (z) is set. clrwdt clear watchdog timer syntax: [ label ] clrwdt operands: none operation: 00h ? wdt 0 ? wdt prescaler, 1 ? to 1 ? pd status affected: to , pd description: clrwdt instruction resets the watch- dog timer. it also resets the prescaler of the wdt. status bits to and pd are set.
? 1998-2013 microchip technology inc. ds30605d-page 103 pic16c63a/65b/73b/74b comf complement f syntax: [ label ] comf f,d operands: 0 ? f ? 127 d ? [0,1] operation: (f ) ? (destination) status affected: z description: the contents of register 'f' are comple- mented. if 'd' is 0, the result is stored in w. if 'd' is 1, the result is stored back in register 'f'. decf decrement f syntax: [ label ] decf f,d operands: 0 ? f ? 127 d ? [0,1] operation: (f) - 1 ? (destination) status affected: z description: decrement register 'f'. if 'd' is 0, the result is stored in the w register. if 'd' is 1, the result is stored back in register 'f'. decfsz decrement f, skip if 0 syntax: [ label ] decfsz f,d operands: 0 ? f ? 127 d ? [0,1] operation: (f) - 1 ? (destination); skip if result = 0 status affected: none description: the contents of register 'f' are decre- mented. if 'd' is 0, the result is placed in the w register. if 'd' is 1, the result is placed back in register 'f'. if the result is 1, the next instruction is executed. if the result is 0, then a nop is executed instead making it a 2 t cy instruction. goto unconditional branch syntax: [ label ] goto k operands: 0 ? k ? 2047 operation: k ? pc<10:0> pclath<4:3> ? pc<12:11> status affected: none description: goto is an unconditional branch. the eleven bit immediate value is loaded into pc bits <10:0>. the upper bits of pc are loaded from pclath<4:3>. goto is a two-cycle instruction. incf increment f syntax: [ label ] incf f,d operands: 0 ? f ? 127 d ? [0,1] operation: (f) + 1 ? (destination) status affected: z description: the contents of register 'f' are incre- mented. if 'd' is 0, the result is placed in the w register. if 'd' is 1, the result is placed back in register 'f'. incfsz increment f, skip if 0 syntax: [ label ] incfsz f,d operands: 0 ? f ? 127 d ? [0,1] operation: (f) + 1 ? (destination), skip if result = 0 status affected: none description: the contents of register 'f' are incre- mented. if 'd' is 0, the result is placed in the w register. if 'd' is 1, the result is placed back in register 'f'. if the result is 1, the next instruction is executed. if the result is 0, a nop is executed instead making it a 2 t cy instruction .
pic16c63a/65b/73b/74b ds30605d-page 104 ? 1998-2013 microchip technology inc. iorlw inclusive or literal with w syntax: [ label ] iorlw k operands: 0 ? k ? 255 operation: (w) .or. k ? (w) status affected: z description: the contents of the w register are or?ed with the eight bit literal 'k'. the result is placed in the w register. iorwf inclusive or w with f syntax: [ label ] iorwf f,d operands: 0 ? f ? 127 d ? [0,1] operation: (w) .or. (f) ? (destination) status affected: z description: inclusive or the w register with regis- ter 'f'. if 'd' is 0 the result is placed in the w register. if 'd' is 1 the result is placed back in register 'f'. movf move f syntax: [ label ] movf f,d operands: 0 ? f ? 127 d ? [0,1] operation: (f) ? (destination) status affected: z description: the contents of register f are moved to a destination dependant upon the status of d. if d = 0, destination is w register. if d = 1, the destination is file register f itself. d = 1 is useful to test a file register since status flag z is affected. movlw move literal to w syntax: [ label ] movlw k operands: 0 ? k ? 255 operation: k ? (w) status affected: none description: the eight bit literal 'k' is loaded into w register. the don?t cares will assemble as 0?s. movwf move w to f syntax: [ label ] movwf f operands: 0 ? f ? 127 operation: (w) ? (f) status affected: none description: move data from w register to register 'f'. nop no operation syntax: [ label ] nop operands: none operation: no operation status affected: none description: no operation.
? 1998-2013 microchip technology inc. ds30605d-page 105 pic16c63a/65b/73b/74b retfie return from interrupt syntax: [ label ] retfie operands: none operation: tos ? pc, 1 ? gie status affected: none retlw return with literal in w syntax: [ label ] retlw k operands: 0 ? k ? 255 operation: k ? (w); tos ? pc status affected: none description: the w register is loaded with the eight bit literal 'k'. the program counter is loaded from the top of the stack (the return address). this is a two-cycle instruction. return return from subroutine syntax: [ label ] return operands: none operation: tos ? pc status affected: none description: return from subroutine. the stack is poped and the top of the stack (tos) is loaded into the program counter. this is a two-cycle instruction. rlf rotate left f through carry syntax: [ label ] rlf f,d operands: 0 ? f ? 127 d ? [0,1] operation: see description below status affected: c description: the contents of register 'f' are rotated one bit to the left through the carry flag. if 'd' is 0, the result is placed in the w register. if 'd' is 1, the result is stored back in register 'f'. rrf rotate right f through carry syntax: [ label ] rrf f,d operands: 0 ? f ? 127 d ? [0,1] operation: see description below status affected: c description: the contents of register 'f' are rotated one bit to the right through the carry flag. if 'd' is 0, the result is placed in the w register. if 'd' is 1, the result is placed back in register 'f'. sleep syntax: [ label ] sleep operands: none operation: 00h ? wdt, 0 ? wdt prescaler, 1 ? to , 0 ? pd status affected: to , pd description: the power-down status bit, pd is cleared. time-out status bit, to is set. watchdog timer and its prescaler are cleared. the processor is put into sleep mode with the oscillator stopped. see section 13.8 for more details. register f c register f c
pic16c63a/65b/73b/74b ds30605d-page 106 ? 1998-2013 microchip technology inc. sublw subtract w from literal syntax: [ label ] sublw k operands: 0 ?? k ?? 255 operation: k - (w) ??? w) status affected: c, dc, z description: the w register is subtracted (2?s com- plement method) from the eight bit lit- eral 'k'. the result is placed in the w register. subwf subtract w from f syntax: [ label ] subwf f,d operands: 0 ?? f ?? 127 d ? [0,1] operation: (f) - (w) ??? destination) status affected: c, dc, z description: subtract (2?s complement method) w register from register 'f'. if 'd' is 0, the result is stored in the w register. if 'd' is 1, the result is stored back in register 'f'. swapf swap nibbles in f syntax: [ label ] swapf f,d operands: 0 ? f ? 127 d ? [0,1] operation: (f<3:0>) ? (destination<7:4>), (f<7:4>) ? (destination<3:0>) status affected: none description: the upper and lower nibbles of regis- ter 'f' are exchanged. if 'd' is 0, the result is placed in w register. if 'd' is 1, the result is placed in register 'f'. xorlw exclusive or literal with w syntax: [ label ] xorlw k operands: 0 ?? k ?? 255 operation: (w) .xor. k ??? w) status affected: z description: the contents of the w register are xor?ed with the eight bit literal 'k'. the result is placed in the w register. xorwf exclusive or w with f syntax: [ label ] xorwf f,d operands: 0 ? f ? 127 d ? [0,1] operation: (w) .xor. (f) ??? destination) status affected: z description: exclusive or the contents of the w register with register 'f'. if 'd' is 0, the result is stored in the w register. if 'd' is 1, the result is stored back in register 'f'.
? 1998-2013 microchip technology inc. ds30605d-page 107 pic16c63a/65b/73b/74b 15.0 development support the pic ? microcontrollers are supported with a full range of hardware and software development tools: ? integrated development environment - mplab ? ide software ? assemblers/compilers/linkers - mpasm tm assembler - mplab c17 and mplab c18 c compilers -mplink tm object linker/ mplib tm object librarian ? simulators - mplab sim software simulator ?emulators - mplab ice 2000 in-circuit emulator - icepic? in-circuit emulator ? in-circuit debugger - mplab icd for pic16f87x ? device programmers -pro mate ? ii universal device programmer - picstart ? plus entry-level development programmer ? low cost demonstration boards - picdem tm 1 demonstration board - picdem 2 demonstration board - picdem 3 demonstration board - picdem 17 demonstration board -k ee l oq ? demonstration board 15.1 mplab integrated development environment software the mplab ide software brings an ease of software development previously unseen in the 8-bit microcon- troller market. the mplab ide is a windows ? -based application that contains: ? an interface to debugging tools - simulator - programmer (sold separately) - emulator (sold separately) - in-circuit debugger (sold separately) ? a full-featured editor ? a project manager ? customizable toolbar and key mapping ? a status bar ? on-line help the mplab ide allows you to: ? edit your source files (either assembly or ?c?) ? one touch assemble (or compile) and download to pic emulator and simulator tools (automatically updates all project information) ? debug using: - source files - absolute listing file - machine code the ability to use mplab ide with multiple debugging tools allows users to easily switch from the cost- effective simulator to a full-featured emulator with minimal retraining. 15.2 mpasm assembler the mpasm assembler is a full-featured universal macro assembler for all pic mcus. the mpasm assembler has a command line interface and a windows shell. it can be used as a stand-alone application on a windows 3.x or greater system, or it can be used through mplab ide. the mpasm assem- bler generates relocatable object files for the mplink object linker, intel ? standard hex files, map files to detail memory usage and symbol reference, an abso- lute lst file that contains source lines and generated machine code, and a cod file for debugging. the mpasm assembler features include: ? integration into mplab ide projects. ? user-defined macros to streamline assembly code. ? conditional assembly for multi-purpose source files. ? directives that allow complete control over the assembly process. 15.3 mplab c17 and mplab c18 c compilers the mplab c17 and mplab c18 code development systems are complete ansi ?c? compilers for microchip?s pic17cxxx and pic18cxxx family of microcontrollers, respectively. these compilers provide powerful integration capabilities and ease of use not found with other compilers. for easier source level debugging, the compilers pro- vide symbol information that is compatible with the mplab ide memory display.
pic16c63a/65b/73b/74b ds30605d-page 108 ? 1998-2013 microchip technology inc. 15.4 mplink object linker/ mplib object librarian the mplink object linker combines relocatable objects created by the mpasm assembler and the mplab c17 and mplab c18 c compilers. it can also link relocatable objects from pre-compiled libraries, using directives from a linker script. the mplib object librarian is a librarian for pre- compiled code to be used with the mplink object linker. when a routine from a library is called from another source file, only the modules that contain that routine will be linked in with the application. this allows large libraries to be used efficiently in many different applications. the mplib object librarian manages the creation and modification of library files. the mplink object linker features include: ? integration with mpasm assembler and mplab c17 and mplab c18 c compilers. ? allows all memory areas to be defined as sections to provide link-time flexibility. the mplib object librarian features include: ? easier linking because single libraries can be included instead of many smaller files. ? helps keep code maintainable by grouping related modules together. ? allows libraries to be created and modules to be added, listed, replaced, deleted or extracted. 15.5 mplab sim software simulator the mplab sim software simulator allows code devel- opment in a pc-hosted environment by simulating the pic series microcontrollers on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a file, or user-defined key press, to any of the pins. the execu- tion can be performed in single step, execute until break, or trace mode. the mplab sim simulator fully supports symbolic debug- ging using the mplab c17 and the mplab c18 c com- pilers and the mpasm assembler. the software simulator offers the flexibility to develop and debug code outside of the laboratory environment, making it an excellent multi- project software development tool. 15.6 mplab ice high performance universal in-circuit emulator with mplab ide the mplab ice universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for pic micro- controllers (mcus). software control of the mplab ice in-circuit emulator is provided by the mplab integrated development environment (ide), which allows editing, building, downloading and source debugging from a single environment. the mplab ice 2000 is a full-featured emulator sys- tem with enhanced trace, trigger and data monitoring features. interchangeable processor modules allow the system to be easily reconfigured for emulation of differ- ent processors. the universal architecture of the mplab ice in-circuit emulator allows expansion to support new pic microcontrollers. the mplab ice in-circuit emulator system has been designed as a real-time emulation system, with advanced features that are generally found on more expensive development tools. the pc platform and microsoft ? windows environment were chosen to best make these features available to you, the end user. 15.7 icepic in-circuit emulator the icepic low cost, in-circuit emulator is a solution for the microchip technology pic16c5x, pic16c6x, pic16c7x and pic16cxxx families of 8-bit one- time-programmable (otp) microcontrollers. the mod- ular system can support different subsets of pic16c5x or pic16cxxx products through the use of inter- changeable personality modules, or daughter boards. the emulator is capable of emulating without target application circuitry being present.
? 1998-2013 microchip technology inc. ds30605d-page 109 pic16c63a/65b/73b/74b 15.8 mplab icd in-circuit debugger microchip's in-circuit debugger, mplab icd, is a pow- erful, low cost, run-time development tool. this tool is based on the flash pic16f87x and can be used to develop for this and other pic microcontrollers from the pic16cxxx family. the mplab icd utilizes the in-cir- cuit debugging capability built into the pic16f87x. this feature, along with microchip's in-circuit serial programming tm protocol, offers cost-effective in-circuit flash debugging from the graphical user interface of the mplab integrated development environment. this enables a designer to develop and debug source code by watching variables, single-stepping and setting break points. running at full speed enables testing hardware in real-time. 15.9 pro mate ii universal device programmer the pro mate ii universal device programmer is a full-featured programmer, capable of operating in stand-alone mode, as well as pc-hosted mode. the pro mate ii device programmer is ce compliant. the pro mate ii device programmer has program- mable v dd and v pp supplies, which allow it to verify programmed memory at v dd min and v dd max for max- imum reliability. it has an lcd display for instructions and error messages, keys to enter commands and a modular detachable socket assembly to support various package types. in stand-alone mode, the pro mate ii device programmer can read, verify, or program pic devices. it can also set code protection in this mode. 15.10 picstart plus entry level development programmer the picstart plus development programmer is an easy-to-use, low cost, prototype programmer. it con- nects to the pc via a com (rs-232) port. mplab integrated development environment software makes using the programmer simple and efficient. the picstart plus development programmer sup- ports all pic devices with up to 40 pins. larger pin count devices, such as the pic16c92x and pic17c76x, may be supported with an adapter socket. the picstart plus development programmer is ce compliant. 15.11 picdem 1 low cost pic mcu demonstration board the picdem 1 demonstration board is a simple board which demonstrates the capabilities of several of microchip?s microcontrollers. the microcontrollers sup- ported are: pic16c5x (pic16c54 to pic16c58a), pic16c61, pic16c62x, pic16c71, pic16c8x, pic17c42, pic17c43 and pic17c44. all necessary hardware and software is included to run basic demo programs. the user can program the sample microcon- trollers provided with the picdem 1 demonstration board on a pro mate ii device programmer, or a picstart plus development programmer, and easily test firmware. the user can also connect the picdem 1 demonstration board to the mplab ice in- circuit emulator and download the firmware to the emu- lator for testing. a prototype area is available for the user to build some additional hardware and connect it to the microcontroller socket(s). some of the features include an rs-232 interface, a potentiometer for simu- lated analog input, push button switches and eight leds connected to portb. 15.12 picdem 2 low cost pic16cxx demonstration board the picdem 2 demonstration board is a simple dem- onstration board that supports the pic16c62, pic16c64, pic16c65, pic16c73 and pic16c74 microcontrollers. all the necessary hardware and soft- ware is included to run the basic demonstration pro- grams. the user can program the sample microcontrollers provided with the picdem 2 demon- stration board on a pro mate ii device programmer, or a picstart plus development programmer, and easily test firmware. the mplab ice in-circuit emula- tor may also be used with the picdem 2 demonstration board to test firmware. a prototype area has been pro- vided to the user for adding additional hardware and connecting it to the microcontroller socket(s). some of the features include a rs-232 interface, push button switches, a potentiometer for simulated analog input, a serial eeprom to demonstrate usage of the i 2 c tm bus and separate headers for connection to an lcd module and a keypad.
pic16c63a/65b/73b/74b ds30605d-page 110 ? 1998-2013 microchip technology inc. 15.13 picdem 3 low cost pic16cxxx demonstration board the picdem 3 demonstration board is a simple dem- onstration board that supports the pic16c923 and pic16c924 in the plcc package. it will also support future 44-pin plcc microcontrollers with an lcd mod- ule. all the necessary hardware and software is included to run the basic demonstration programs. the user can program the sample microcontrollers pro- vided with the picdem 3 demonstration board on a pro mate ii device programmer, or a picstart plus development programmer with an adapter socket, and easily test firmware. the mplab ice in-circuit emula- tor may also be used with the picdem 3 demonstration board to test firmware. a prototype area has been pro- vided to the user for adding hardware and connecting it to the microcontroller socket(s). some of the features include a rs-232 interface, push button switches, a potentiometer for simulated analog input, a thermistor and separate headers for connection to an external lcd module and a keypad. also provided on the picdem 3 demonstration board is a lcd panel, with 4 commons and 12 segments, that is capable of display- ing time, temperature and day of the week. the picdem 3 demonstration board provides an additional rs-232 interface and windows software for showing the demultiplexed lcd signals on a pc. a simple serial interface allows the user to construct a hardware demultiplexer for the lcd signals. 15.14 picdem 17 demonstration board the picdem 17 demonstration board is an evaluation board that demonstrates the capabilities of several microchip microcontrollers, including pic17c752, pic17c756a, pic17c762 and pic17c766. all neces- sary hardware is included to run basic demo programs, which are supplied on a 3.5-inch disk. a programmed sample is included and the user may erase it and program it with the other sample programs using the pro mate ii device programmer, or the picstart plus development programmer, and easily debug and test the sample code. in addition, the picdem 17 dem- onstration board supports downloading of programs to and executing out of external flash memory on board. the picdem 17 demonstration board is also usable with the mplab ice in-circuit emulator, or the picmaster emulator and all of the sample programs can be run and modified using either emulator. addition- ally, a generous prototype area is available for user hardware. 15.15 k ee l oq evaluation and programming tools k ee l oq evaluation and programming tools support microchip?s hcs secure data products. the hcs eval- uation kit includes a lcd display to show changing codes, a decoder to decode transmissions and a pro- gramming interface to program test transmitters.
? 1998-2013 microchip technology inc. ds30605d-page 111 pic16c63a/65b/73b/74b table 15-1: development tools from microchip pic12cxxx pic14000 pic16c5x pic16c6x pic16cxxx pic16f62x pic16c7x pic16c7xx pic16c8x pic16f8xx pic16c9xx pic17c4x pic17c7xx pic18cxx2 24cxx/ 25cxx/ 93cxx hcsxxx mcrfxxx mcp2510 software tools mplab ? integrated development environment ?????????????? mplab ? c17 c compiler ?? mplab ? c18 c compiler ? mpasm tm assembler/ mplink tm object linker ???????????????? emulators mplab ? ice in-circuit emulator ?????? ** ???????? icepic tm in-circuit emulator ? ??? ??? ? debugger mplab ? icd in-circuit debugger ? * ? * ? programmers picstart ? plus entry level development programmer ?????? ** ???????? pro mate ? ii universal device programmer ?????? ** ?????????? demo boards and eval kits picdem tm 1 demonstration board ??? ? ?? picdem tm 2 demonstration board ? ? ? ? ? picdem tm 3 demonstration board ? picdem tm 14a demonstration board ? picdem tm 17 demonstration board ? k ee l oq ? evaluation kit ? k ee l oq ? transponder kit ? microid tm programmer?s kit ? 125 khz microid tm developer?s kit ? 125 khz anticollision microid tm developer?s kit ? 13.56 mhz anticollision microid tm developer?s kit ? mcp2510 can developer?s kit ? * contact the microchip technology inc. web site at www.microchip.com for information on how to use the mplab ? icd in-circuit debugger (dv164001) with pic16c62, 63, 64, 65, 72, 73, 74, 76, 77. ** contact microchip technology inc. for availability date. ? development tool is available on select devices.
pic16c63a/65b/73b/74b ds30605d-page 112 ? 1998-2013 microchip technology inc. notes:
? 1998-2013 microchip technology inc. ds30605d-page 113 pic16c63a/65b/73b/74b 16.0 electrical characteristics absolute maximum ratings (?) ambient temperature under bias................................................................................................. ............-55c to +125c storage temperature ............................................................................................................ .................. -65c to +150c voltage on any pin with respect to v ss (except v dd , mclr and ra4) .......................................... -0.3v to (v dd + 0.3v) voltage on v dd with respect to v ss ......................................................................................................... -0.3v to +7.5v voltage on mclr with respect to v ss (note 2) ......................................................................................... 0v to +13.25v voltage on ra4 with respect to v ss ............................................................................................................... 0v to +8.5v total power dissipation (note 1) ............................................................................................................................... 1.0w maximum current out of v ss pin ........................................................................................................................... 300 ma maximum current into v dd pin ........................................................................................................................... ...250 ma input clamp current, i ik (v i < 0 or v i > v dd ) .......................................................................................................... 20 ma output clamp current, i ok (v o < 0 or v o > v dd ) ...................................................................................................20 ma maximum output current sunk by any i/o pin..................................................................................... .....................25 ma maximum output current sourced by any i/o pin .................................................................................. ..................25 ma maximum current sunk by porta, portb, and porte (note 3) (combined)...................................................200 ma maximum current sourced by porta, portb, and porte (note 3) (combined)..............................................200 ma maximum current sunk by portc and portd (note 3) (combined)..................................................................200 ma maximum current sourced by portc and portd (note 3) (combined).............................................................200 ma note 1: power dissipation is calculated as follows: pdis = v dd x {i dd - ? i oh } + ? {(v dd -v oh ) x i oh } + ? (v o l x i ol ) 2: voltage spikes below v ss at the mclr /v pp pin, inducing currents greater than 80 ma, may cause latch-up. thus, a series resistor of 50 - 100 ? should be used when applying a ?low? level to the mclr /v pp pin rather than pulling this pin directly to v ss . 3: portd and porte not available on the pic16c63a/73b. ? notice: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
pic16c63a/65b/73b/74b ds30605d-page 114 ? 1998-2013 microchip technology inc. figure 16-1: pic16c63a/65b/73b/74b voltag e-frequency graph figure 16-2: pic16lc63a/65b/73b/74b vo ltage-frequency graph frequency voltage 6.0 v 5.5 v 4.5 v 4.0 v 2.0 v 20 mhz 5.0 v 3.5 v 3.0 v 2.5 v pic16cxxx-20 frequency voltage 6.0 v 5.5 v 4.5 v 4.0 v 2.0 v 5.0 v 3.5 v 3.0 v 2.5 v f max = (12.0 mhz/v) (v ddappmin - 2.5 v) + 4 mhz note 1: v ddappmin is the minimum voltage of the pic ? device in the application. 4 mhz 10 mhz note 2: f max has a maximum frequency of 10mhz. pic16lcxxx-04
? 1998-2013 microchip technology inc. ds30605d-page 115 pic16c63a/65b/73b/74b figure 16-3: pic16c63a/65b/73b/74b voltag e-frequency graph frequency voltage 6.0 v 5.5 v 4.5 v 4.0 v 2.0 v 5.0 v 3.5 v 3.0 v 2.5 v pic16cxxx-04 4 mhz
pic16c63a/65b/73b/74b ds30605d-page 116 ? 1998-2013 microchip technology inc. 16.1 dc characteristics pic16lc63a/65b/73b/74b-04 standard operating conditions (unless otherwise stated) operating temperature 0c ? t a ? +70c for commercial -40c ? t a ? +85c for industrial ? pic16c63a/65b/73b/74b-04 ? pic16c6a/65b/73b/74b-20 standard operating conditions (unless otherwise stated) operating temperature 0c ? t a ? +70c for commercial -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. sym characteristic min typ? max units conditions v dd supply voltage d001 pic16lcxxx 2.5 v bor * ? ? 5.5 5.5 v v lp, xt, rc osc modes (dc - 4 mhz) bor enabled (note 7) d001 d001a pic16cxxx 4.0 4.5 v bor * ? ? ? 5.5 5.5 5.5 v v v xt, rc and lp osc mode hs osc mode bor enabled (note 7) d002* v dr ram data retention voltage (note 1) ?1.5? v d003 v por v dd start voltage to ensure internal power-on reset signal ?v ss ? v see section on power-on reset for details d004* d004a* s vdd v dd rise rate to ensure internal power-on reset signal 0.05 tbd ? ? ? ? v/ms v/ms pwrt enabled (pwrte bit clear) pwrt disabled (pwrte bit set) see section on power-on reset for details d005 v bor brown-out reset voltage trip point 3.65 ? 4.35 v boden bit set * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. ? when specification values of standard devices differ from those of extended voltage devices, they are shown in gray. note 1: this is the limit to which v dd can be lowered without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tri-stated, pulled to v dd , mclr = v dd ; wdt enabled/disabled as specified. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is mea- sured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss . 4: for rc osc mode, current through r ext is not included. the current through the resistor can be estimated by the formula ir = v dd /2r ext (ma) with r ext in kohm. 5: timer1 oscillator (when enabled) adds approximately 20 ? a to the specification. this value is from character- ization and is for design guidance only. this is not tested. 6: the ? current is the additional current consumed when this peripheral is enabled. this current should be added to the base i dd or i pd measurement. 7: when bor is enabled, the device will operate correctly until the v bor voltage trip point is reached. 8: in rc oscillator mode, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic device be driven with external clock in rc mode. 9: the leakage current on the mclr /v pp pin is strongly dependent on the applied voltage level. the specified lev- els represent normal operating conditions. higher leaka ge current may be measured at different input voltages. 10: negative current is defined as current sourced by the pin.
? 1998-2013 microchip technology inc. ds30605d-page 117 pic16c63a/65b/73b/74b i dd supply current (notes 2, 5) d010 d010a pic16lcxxx ? ? 0.6 22.5 2.0 48 ma ? a xt, rc osc modes: f osc = 4 mhz, v dd = 3.0v (note 4) lp osc mode: f osc = 32 khz, v dd = 3.0v, wdt disabled d010 d013 pic16cxxx ? ? 2.7 7 5 10 ma ma xt, rc osc modes: f osc = 4 mhz, v dd = 5.5 v (note 4) hs osc mode: f osc = 20 mhz, v dd = 5.5 v i pd power-down current (notes 3, 5) d020 d021 d021a pic16lcxxx ? ? ? 7.5 0.9 0.9 20 3 3 ? a ? a ? a v dd = 3.0v, wdt enabled, -40c to +85c v dd = 3.0v, wdt disabled, 0c to +70c v dd = 3.0v, wdt disabled, -40c to +85c d020 d021 d021a d021b pic16cxxx ? ? ? ? 10.5 1.5 1.5 2.5 42 16 19 19 ? a ? a ? a ? a v dd = 4.0v, wdt enabled, -40c to +85c v dd = 4.0v, wdt disabled, 0c to +70c v dd = 4.0v, wdt disabled, -40c to +85c v dd = 4.0v, wdt disabled, -40c to +125c pic16lc63a/65b/73b/74b-04 standard operating conditions (unless otherwise stated) operating temperature 0c ? t a ? +70c for commercial -40c ? t a ? +85c for industrial ? pic16c63a/65b/73b/74b-04 ? pic16c6a/65b/73b/74b-20 standard operating conditions (unless otherwise stated) operating temperature 0c ? t a ? +70c for commercial -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. sym characteristic min typ? max units conditions * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. ? when specification values of standard devices differ from those of extended voltage devices, they are shown in gray. note 1: this is the limit to which v dd can be lowered without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tri-stated, pulled to v dd , mclr = v dd ; wdt enabled/disabled as specified. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is mea- sured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss . 4: for rc osc mode, current through r ext is not included. the current through the resistor can be estimated by the formula ir = v dd /2r ext (ma) with r ext in kohm. 5: timer1 oscillator (when enabled) adds approximately 20 ? a to the specification. this value is from character- ization and is for design guidance only. this is not tested. 6: the ? current is the additional current consumed when this peripheral is enabled. this current should be added to the base i dd or i pd measurement. 7: when bor is enabled, the device will operate correctly until the v bor voltage trip point is reached. 8: in rc oscillator mode, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic device be driven with external clock in rc mode. 9: the leakage current on the mclr /v pp pin is strongly dependent on the applied voltage level. the specified lev- els represent normal operating conditions. higher leaka ge current may be measured at different input voltages. 10: negative current is defined as current sourced by the pin.
pic16c63a/65b/73b/74b ds30605d-page 118 ? 1998-2013 microchip technology inc. module differential current (note 6) d022* ? i wdt watchdog timer ? 6.0 20 ? a wdte bit set, v dd = 4.0v d022a* ? i bor brown-out reset ? 100 150 ? a boden bit set, v dd = 5.0 input low voltage v il i/o ports d030 d030a with ttl buffer v ss v ss ? ? 0.15 v dd 0.8v v v for entire v dd range 4.5v ? v dd ? 5.5v d031 with schmitt trigger buffer v ss ?0.2v dd v d032 mclr , osc1 (in rc mode) vss ? 0.2 v dd v d033 osc1 (in xt, hs, and lp modes) vss ? 0.3 v dd v (note 8) pic16lc63a/65b/73b/74b-04 standard operating conditions (unless otherwise stated) operating temperature 0c ? t a ? +70c for commercial -40c ? t a ? +85c for industrial ? pic16c63a/65b/73b/74b-04 ? pic16c6a/65b/73b/74b-20 standard operating conditions (unless otherwise stated) operating temperature 0c ? t a ? +70c for commercial -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. sym characteristic min typ? max units conditions * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. ? when specification values of standard devices differ from those of extended voltage devices, they are shown in gray. note 1: this is the limit to which v dd can be lowered without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tri-stated, pulled to v dd , mclr = v dd ; wdt enabled/disabled as specified. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is mea- sured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss . 4: for rc osc mode, current through r ext is not included. the current through the resistor can be estimated by the formula ir = v dd /2r ext (ma) with r ext in kohm. 5: timer1 oscillator (when enabled) adds approximately 20 ? a to the specification. this value is from character- ization and is for design guidance only. this is not tested. 6: the ? current is the additional current consumed when this peripheral is enabled. this current should be added to the base i dd or i pd measurement. 7: when bor is enabled, the device will operate correctly until the v bor voltage trip point is reached. 8: in rc oscillator mode, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic device be driven with external clock in rc mode. 9: the leakage current on the mclr /v pp pin is strongly dependent on the applied voltage level. the specified lev- els represent normal operating conditions. higher leaka ge current may be measured at different input voltages. 10: negative current is defined as current sourced by the pin.
? 1998-2013 microchip technology inc. ds30605d-page 119 pic16c63a/65b/73b/74b input high voltage v ih i/o ports d040 with ttl buffer 2.0 ?v dd v4.5v ? v dd ? 5.5v d040a 0.25 v dd + 0.8v ?v dd v for entire v dd range d041 with schmitt trigger buffer 0.8 v dd ?v dd v for entire v dd range d042 mclr 0.8 v dd ?v dd v d042a osc1 (in xt, hs, and lp modes) 0.7 v dd ?v dd v (note 8) d043 osc1 (in rc mode) 0.9 v dd ?v dd v input leakage current (notes 9, 10) d060 i il i/o ports ? ? 1 ? avss ? v pin ? v dd , pin at hi-impedance d061 mclr , ra4/t0cki ? ? 5 ? avss ? v pin ? v dd d063 osc1 ? ? 5 ? avss ? v pin ? v dd , xt, hs and lp osc modes d070 i purb portb weak pull-up current 50 250 400 ? av dd = 5v, v pin = v ss pic16lc63a/65b/73b/74b-04 standard operating conditions (unless otherwise stated) operating temperature 0c ? t a ? +70c for commercial -40c ? t a ? +85c for industrial ? pic16c63a/65b/73b/74b-04 ? pic16c6a/65b/73b/74b-20 standard operating conditions (unless otherwise stated) operating temperature 0c ? t a ? +70c for commercial -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. sym characteristic min typ? max units conditions * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. ? when specification values of standard devices differ from those of extended voltage devices, they are shown in gray. note 1: this is the limit to which v dd can be lowered without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tri-stated, pulled to v dd , mclr = v dd ; wdt enabled/disabled as specified. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is mea- sured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss . 4: for rc osc mode, current through r ext is not included. the current through the resistor can be estimated by the formula ir = v dd /2r ext (ma) with r ext in kohm. 5: timer1 oscillator (when enabled) adds approximately 20 ? a to the specification. this value is from character- ization and is for design guidance only. this is not tested. 6: the ? current is the additional current consumed when this peripheral is enabled. this current should be added to the base i dd or i pd measurement. 7: when bor is enabled, the device will operate correctly until the v bor voltage trip point is reached. 8: in rc oscillator mode, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic device be driven with external clock in rc mode. 9: the leakage current on the mclr /v pp pin is strongly dependent on the applied voltage level. the specified lev- els represent normal operating conditions. higher leaka ge current may be measured at different input voltages. 10: negative current is defined as current sourced by the pin.
pic16c63a/65b/73b/74b ds30605d-page 120 ? 1998-2013 microchip technology inc. output low voltage d080 v ol i/o ports ? ? 0.6 v i ol = 8.5 ma, v dd = 4.5v, -40c to +85c ??0.6vi ol = 7.0 ma, v dd = 4.5v, -40c to +125c d083 osc2/clkout (rc osc mode) ??0.6vi ol = 1.6 ma, v dd = 4.5v, -40c to +85c ??0.6vi ol = 1.2 ma, v dd = 4.5v, -40c to +125c output high voltage d090 v oh i/o ports (note 10) v dd -0.7 ? ? v i oh = -3.0 ma, v dd = 4.5v, -40c to +85c v dd -0.7 ? ? v i oh = -2.5 ma, v dd = 4.5v, -40c to +125c d092 osc2/clkout (rc osc mode) v dd -0.7 ? ? v i oh = -1.3 ma, v dd = 4.5v, -40c to +85c v dd -0.7 ? ? v i oh = -1.0 ma, v dd = 4.5v, -40c to +125c d150* v od open-drain high voltage ? ? 8.5 v ra4 pin pic16lc63a/65b/73b/74b-04 standard operating conditions (unless otherwise stated) operating temperature 0c ? t a ? +70c for commercial -40c ? t a ? +85c for industrial ? pic16c63a/65b/73b/74b-04 ? pic16c6a/65b/73b/74b-20 standard operating conditions (unless otherwise stated) operating temperature 0c ? t a ? +70c for commercial -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. sym characteristic min typ? max units conditions * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. ? when specification values of standard devices differ from those of extended voltage devices, they are shown in gray. note 1: this is the limit to which v dd can be lowered without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tri-stated, pulled to v dd , mclr = v dd ; wdt enabled/disabled as specified. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is mea- sured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss . 4: for rc osc mode, current through r ext is not included. the current through the resistor can be estimated by the formula ir = v dd /2r ext (ma) with r ext in kohm. 5: timer1 oscillator (when enabled) adds approximately 20 ? a to the specification. this value is from character- ization and is for design guidance only. this is not tested. 6: the ? current is the additional current consumed when this peripheral is enabled. this current should be added to the base i dd or i pd measurement. 7: when bor is enabled, the device will operate correctly until the v bor voltage trip point is reached. 8: in rc oscillator mode, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic device be driven with external clock in rc mode. 9: the leakage current on the mclr /v pp pin is strongly dependent on the applied voltage level. the specified lev- els represent normal operating conditions. higher leaka ge current may be measured at different input voltages. 10: negative current is defined as current sourced by the pin.
? 1998-2013 microchip technology inc. ds30605d-page 121 pic16c63a/65b/73b/74b capacitive loading specs on output pins d100 c osc2 osc2 pin ? ? 15 pf in xt, hs and lp modes when external clock is used to drive osc1 d101 c io all i/o pins and osc2 (in rc mode) ??50pf d102 cb scl, sda (in i 2 c mode) ??400pf pic16lc63a/65b/73b/74b-04 standard operating conditions (unless otherwise stated) operating temperature 0c ? t a ? +70c for commercial -40c ? t a ? +85c for industrial ? pic16c63a/65b/73b/74b-04 ? pic16c6a/65b/73b/74b-20 standard operating conditions (unless otherwise stated) operating temperature 0c ? t a ? +70c for commercial -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. sym characteristic min typ? max units conditions * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. ? when specification values of standard devices differ from those of extended voltage devices, they are shown in gray. note 1: this is the limit to which v dd can be lowered without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tri-stated, pulled to v dd , mclr = v dd ; wdt enabled/disabled as specified. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is mea- sured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss . 4: for rc osc mode, current through r ext is not included. the current through the resistor can be estimated by the formula ir = v dd /2r ext (ma) with r ext in kohm. 5: timer1 oscillator (when enabled) adds approximately 20 ? a to the specification. this value is from character- ization and is for design guidance only. this is not tested. 6: the ? current is the additional current consumed when this peripheral is enabled. this current should be added to the base i dd or i pd measurement. 7: when bor is enabled, the device will operate correctly until the v bor voltage trip point is reached. 8: in rc oscillator mode, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic device be driven with external clock in rc mode. 9: the leakage current on the mclr /v pp pin is strongly dependent on the applied voltage level. the specified lev- els represent normal operating conditions. higher leaka ge current may be measured at different input voltages. 10: negative current is defined as current sourced by the pin.
pic16c63a/65b/73b/74b ds30605d-page 122 ? 1998-2013 microchip technology inc. 16.2 ac (timing) characteristics 16.2.1 timing parameter symbology the timing parameter symbols have been created following one of the following formats: 1. tpps2pps 3. t cc : st (i 2 c specifications only) 2. tpps 4. ts (i 2 c specifications only) t f frequency t time lowercase letters (pp) and their meanings: pp cc ccp1 osc osc1 ck clkout rd rd cs cs rw rd or wr di sdi sc sck do sdo ss ss dt data in t0 t0cki io i/o port t1 t1cki mc mclr wr wr uppercase letters and their meanings: s f fall p period hhigh rrise i invalid (hi-impedance) v valid l low z hi-impedance i 2 c only aa output access high high buf bus free low low t cc : st (i 2 c specifications only) cc hd hold su setup st dat data input hold sto stop condition sta start condition
? 1998-2013 microchip technology inc. ds30605d-page 123 pic16c63a/65b/73b/74b 16.2.2 timing conditions the temperature and voltages specified in table 16-1 apply to all timing specifications unless otherwise noted. figure 16-4 specifies the load conditions for the timing specifications. table 16-1: temperature and vo ltage specifications - ac figure 16-4: load conditions for device timing specifications ac characteristics standard operating conditions (unless otherwise stated) operating temperature 0c ? t a ? +70c for commercial -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended operating voltage v dd range as described in dc spec section 16.1. lc parts operate for commercial/industrial temperatures only. v dd /2 c l r l pin pin v ss v ss c l r l = 464 ? c l = 50 pf for all pins except osc2/clkout but including d and e outputs as ports c l = 15 pf for osc2 output load condition 1 load condition 2 note 1: portd and porte are not implemented on the pic16c63a/73b.
pic16c63a/65b/73b/74b ds30605d-page 124 ? 1998-2013 microchip technology inc. 16.2.3 timing diagrams and specifications figure 16-5: extern al clock timing table 16-2: external clock timing requirements param no. sym characteristic min typ? max units conditions 1a f osc external clkin frequency (note 1) dc ? 4 mhz rc and xt osc modes dc ? 4 mhz hs osc mode (-04) dc ? 20 mhz hs osc mode (-20) dc ? 200 khz lp osc mode oscillator frequency (note 1) dc ? 4 mhz rc osc mode 0.1 ? 4 mhz xt osc mode 4 ? 20 mhz hs osc mode 5 ? 200 khz lp osc mode 1 t osc external clkin period (note 1) 250 ? ? ns rc and xt osc modes 250 ? ? ns hs osc mode (-04) 50 ? ? ns hs osc mode (-20) 5? ? ? slp osc mode oscillator period (note 1) 250 ? ? ns rc osc mode 250 ? 10,000 ns xt osc mode 250 ? 250 ns hs osc mode (-04) 50 ? 250 ns hs osc mode (-20) 5? ? ? slp osc mode 2 t cy instruction cycle time (note 1) 200 ? dc ns t cy = 4/f osc 3* to sl , to s h external clock in (osc1) high or low time 100 ? ? ns xt oscillator 2.5 ? ? ? s lp oscillator 15 ? ? ns hs oscillator 4* tos r , to s f external clock in (osc1) rise or fall time ? ? 25 ns xt oscillator ? ? 50 ns lp oscillator ? ? 15 ns hs oscillator * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: instruction cycle period (t cy ) equals four times the input oscillator time-base period. all specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. all devices are tested to operate at ?min.? values with an external clock applied to the osc1/clkin pin. when an external clock input is used, the ?max.? cycle time limit is ?dc? (no clock) for all devices. 3 3 4 4 1 2 q4 q1 q2 q3 q4 q1 osc1 clkout
? 1998-2013 microchip technology inc. ds30605d-page 125 pic16c63a/65b/73b/74b figure 16-6: clko ut and i/o timing table 16-3: clkout and i/o timing requirements note: refer to figure 16-4 for load conditions. osc1 clkout i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 19 18 15 11 12 16 old value new value param no. sym characteristic min typ? max units conditions 10* tosh2ckl osc1 ? to clkout ? ? 75 200 ns (note 1) 11* tosh2ckh osc1 ? to clkout ? ? 75 200 ns (note 1) 12* tckr clkout rise time ? 35 100 ns (note 1) 13* tckf clkout fall time ? 35 100 ns (note 1) 14* tckl2iov clkout ? to port out valid ? ? 0.5t cy + 20 ns (note 1) 15* tiov2ckh port in valid before clkout ? t osc + 200 ? ? ns (note 1) 16* tckh2ioi port in hold after clkout ? 0?? ns (note 1) 17* tosh2iov osc1 ? (q1 cycle) to port out valid ? 50 150 ns 18* tosh2ioi osc1 ? (q2 cycle) to port input invalid (i/o in hold time) pic16cxx 100 ? ? ns 18a* pic16lcxx 200 ? ? ns 19* tiov2osh port input valid to osc1 ?? (i/o in setup time) 0?? ns 20* tior port output rise time pic16cxx ? 10 40 ns 20a* pic16lcxx ? ? 80 ns 21* tiof port output fall time pic16cxx ? 10 40 ns 21a* pic16lcxx ? ? 80 ns 22??* tinp int pin high or low time t cy ??ns 23??* trbp rb7:rb4 change int high or low time t cy ??ns * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. ??these parameters are asynchronous events not related to any internal clock edge. note 1: measurements are taken in rc mode where clkout output is 4 x t osc .
pic16c63a/65b/73b/74b ds30605d-page 126 ? 1998-2013 microchip technology inc. figure 16-7: reset, watchdog timer, os cillator start-up timer and power-up timer timing figure 16-8: brown-out reset timing table 16-4: reset, watchdog timer, oscill ator start-up timer, power-up timer, and brown-out reset requirements v dd mclr internal por pwrt time-out osc time-out internal reset watchdog timer reset 33 32 30 31 34 i/o pins 34 note: refer to figure 16-4 for load conditions. v dd bv dd 35 param no. sym characteristic min typ? max units conditions 30 tmcl mclr pulse width (low) 2 ? ? ? sv dd = 5v, -40c to +125c 31* t wdt watchdog timer time-out period (no prescaler) 71833msv dd = 5v, -40c to +125c 32 t ost oscillation start-up timer period ? 1024 t osc ??t osc = osc1 period 33* t pwrt power-up timer period 28 72 132 ms v dd = 5v, -40c to +125c 34 t ioz i/o hi-impedance from mclr low or wdt reset ??2.1 ? s 35 t bor brown-out reset pulse width 100 ? ? ? sv dd ? b vdd (d005) * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested.
? 1998-2013 microchip technology inc. ds30605d-page 127 pic16c63a/65b/73b/74b figure 16-9: timer0 and timer1 external clock timings table 16-5: timer0 and timer1 external clock requirements param no. sym characteristic min typ? max units conditions 40* tt0h t0cki high pulse width no prescaler 0.5t cy + 20 ? ? ns must also meet parameter 42 with prescaler 10 ? ? ns 41* tt0l t0cki low pulse width no prescaler 0.5t cy + 20 ? ? ns must also meet parameter 42 with prescaler 10 ? ? ns 42* tt0p t0cki period no prescaler t cy + 40 ? ? ns with prescaler greater of: 20 or t cy + 40 n ? ? ns n = prescale value (2, 4,..., 256) 45* tt1h t1cki high time synchronous, prescaler = 1 0.5t cy + 20 ? ? ns must also meet parameter 47 synchronous, prescaler = 2,4,8 pic16cxx 15 ? ? ns pic16lcxx 25 ? ? ns asynchronous pic16cxx 30 ? ? ns pic16lcxx 50 ? ? ns 46* tt1l t1cki low time synchronous, prescaler = 1 0.5t cy + 20 ? ? ns must also meet parameter 47 synchronous, prescaler = 2,4,8 pic16cxx 15 ? ? ns pic16lcxx 25 ? ? ns asynchronous pic16cxx 30 ? ? ns pic16lcxx 50 ? ? ns 47* tt1p t1cki input period synchronous pic16cxx greater of : 30 or t cy + 40 n ? ? ns n = prescale value (1, 2, 4, 8) pic16lcxx greater of : 50 or t cy + 40 n n = prescale value (1, 2, 4, 8) asynchronous pic16cxx 60 ? ? ns pic16lcxx 100 ? ? ns ft1 timer1 oscillator input frequency range (oscillator enabled by setting bit t1oscen) dc ? 200 khz 48 tckeztmr1 delay from external clock edge to timer increment 2t osc ?7t osc ? * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 16-4 for load conditions. 46 47 45 48 41 42 40 t0cki t1oso/t1cki tmr0 or tmr1
pic16c63a/65b/73b/74b ds30605d-page 128 ? 1998-2013 microchip technology inc. figure 16-10: capture/compare /pwm timings (ccp1 and ccp2) table 16-6: capture/compare/pwm requirements (ccp1 and ccp2) note: refer to figure 16-4 for load conditions. ccpx (capture mode) 50 51 52 ccpx 53 54 (compare or pwm mode) param no. sym characteristic min typ? max units conditions 50* tccl ccp1 and ccp2 input low time no prescaler 0.5t cy + 20 ? ? ns with prescaler pic16cxx 10 ? ? ns pic16lcxx 20 ? ? ns 51* tcch ccp1 and ccp2 input high time no prescaler 0.5t cy + 20 ? ? ns with prescaler pic16cxx 10 ? ? ns pic16lcxx 20 ? ? ns 52* tccp ccp1 and ccp2 input period 3t cy + 40 n ? ? ns n = prescale value (1,4, or 16) 53* tccr ccp1 and ccp2 output rise time pic16cxx ? 10 25 ns pic16lcxx ? 25 45 ns 54* tccf ccp1 and ccp2 output fall time pic16cxx ? 10 25 ns pic16lcxx ? 25 45 ns * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested.
? 1998-2013 microchip technology inc. ds30605d-page 129 pic16c63a/65b/73b/74b figure 16-11: parallel slave po rt timing (pic16c65b/74b) table 16-7: parallel slave port requirements (pic16c65b/74b) note: refer to figure 16-4 for load conditions. re2/cs re0/rd re1/wr rd7:rd0 62 63 64 65 param no. sym characteristic min typ? max units conditions 62* tdtv2wrh data in valid before wr ? or cs ? (setup time) 20 ? ? ns 63* twrh2dti wr ? or cs ? to data in invalid (hold time) pic16cxx 20 ? ? ns pic16lcxx 35 ? ? ns 64 trdl2dtv rd ? and cs ? to data out valid ??80 ns 65* trdh2dti rd ? or cs ? to data out invalid 10 ? 30 ns * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested.
pic16c63a/65b/73b/74b ds30605d-page 130 ? 1998-2013 microchip technology inc. figure 16-12: example spi master mode timing (cke = 0) table 16-8: example spi mode requirements (master mode, cke = 0) param no. symbol characteristic min typ? max units conditions 70 tssl2sch, tssl2scl ss ? to sck ? or sck ? input t cy ?? ns 71 tsch sck input high time (slave mode) continuous 1.25t cy + 30 ? ? ns 71a single byte 40 ? ? ns (note 1) 72 tscl sck input low time (slave mode) continuous 1.25t cy + 30 ? ? ns 72a single byte 40 ? ? ns (note 1) 73 tdiv2sch, tdiv2scl setup time of sdi data input to sck edge 100 ? ? ns 73a t b 2 b last clock edge of byte1 to the 1st clock edge of byte2 1.5t cy + 40 ? ? ns (note 1) 74 tsch2dil, tscl2dil hold time of sdi data input to sck edge 100 ? ? ns 75 tdor sdo data output rise time pic16cxx ?1025ns pic16lcxx ?2045ns 76 tdof sdo data output fall time ?1025ns 78 tscr sck output rise time (master mode) pic16cxx ?1025ns pic16lcxx ?2045ns 79 tscf sck output fall time (master mode) ?1025ns 80 tsch2dov, tscl2dov sdo data output valid after sck edge pic16cxx ??50ns pic16lcxx ? ? 100 ns ? data in ?typ? column is at 5 v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: specification 73a is only required if specifications 71a and 72a are used. ss sck (ckp = 0) sck (ckp = 1) sdo sdi 70 71 72 73 74 75, 76 78 79 80 79 78 msb lsb bit6 - - - - - -1 msb in lsb in bit6 - - - -1 note: refer to figure 16-4 for load conditions.
? 1998-2013 microchip technology inc. ds30605d-page 131 pic16c63a/65b/73b/74b figure 16-13: example spi master mode timing (cke = 1) table 16-9: example spi mode requirements (master mode, cke = 1) ss sck (ckp = 0) sck (ckp = 1) sdo sdi 81 71 72 74 75, 76 78 80 msb 79 73 msb in bit6 - - - - - -1 lsb in bit6 - - - -1 lsb note: refer to figure 16-4 for load conditions. param no. symbol characteristic min typ? max units conditions 71 tsch sck input high time (slave mode) continuous 1.25t cy + 30 ? ? ns 71a single byte 40 ? ? ns (note 1) 72 tscl sck input low time (slave mode) continuous 1.25t cy + 30 ? ? ns 72a single byte 40 ? ? ns (note 1) 73 tdiv2sch, tdiv2scl setup time of sdi data input to sck edge 100 ? ? ns 73a t b 2 b last clock edge of byte1 to the 1st clock edge of byte2 1.5t cy + 40 ? ? ns (note 1) 74 ts c h 2 d i l , ts c l 2 d i l hold time of sdi data input to sck edge 100 ? ? ns 75 tdor sdo data output rise time pic16cxx ? 10 25 ns pic16lcxx 20 45 ns 76 tdof sdo data output fall time ? 10 25 ns 78 tscr sck output rise time (master mode) pic16cxx ? 10 25 ns pic16lcxx 20 45 ns 79 tscf sck output fall time (master mode) ? 10 25 ns 80 tsch2dov, tscl2dov sdo data output valid after sck edge pic16cxx ? ? 50 ns pic16lcxx ? 100 ns 81 tdov2sch, tdov2scl sdo data output setup to sck edge t cy ?? ns ? data in ?typ? column is at 5 v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: specification 73a is only required if specifications 71a and 72a are used.
pic16c63a/65b/73b/74b ds30605d-page 132 ? 1998-2013 microchip technology inc. figure 16-14: example spi slave mode timing (cke = 0) table 16-10: example spi mode requirements (slave mode timing (cke = 0) param no. symbol characteristic min typ? max units conditions 70 tssl2sch, tssl2scl ss ? to sck ? or sck ? input t cy ?? ns 71 tsch sck input high time (slave mode) continuous 1.25t cy + 30 ? ? ns 71a single byte 40 ? ? ns (note 1) 72 tscl sck input low time (slave mode) continuous 1.25t cy + 30 ? ? ns 72a single byte 40 ? ? ns (note 1) 73 tdiv2sch, tdiv2scl setup time of sdi data input to sck edge 100 ? ? ns 73a t b 2 b last clock edge of byte1 to the 1st clock edge of byte2 1.5t cy + 40 ? ? ns (note 1) 74 tsch2dil, tscl2dil hold time of sdi data input to sck edge 100 ? ? ns 75 tdor sdo data output rise time pic16cxx ? 10 25 ns pic16lcxx 20 45 ns 76 tdof sdo data output fall time ? 10 25 ns 77 tssh2doz ss ? to sdo output hi-impedance 10 ? 50 ns 78 tscr sck output rise time (master mode) pic16cxx ? 10 25 ns pic16lcxx 20 45 ns 79 tscf sck output fall time (master mode) ? 10 25 ns 80 tsch2dov, tscl2dov sdo data output valid after sck edge pic16cxx ? ? 50 ns pic16lcxx ? 100 ns 83 tsch2ssh, tscl2ssh ss ? after sck edge 1.5t cy + 40 ? ? ns ? data in ?typ? column is at 5 v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: specification 73a is only required if specifications 71a and 72a are used. ss sck (ckp = 0) sck (ckp = 1) sdo sdi 70 71 72 73 74 75, 76 77 78 79 80 79 78 sdi msb lsb bit6 - - - - - -1 msb in bit6 - - - -1 lsb in 83 note: refer to figure 16-4 for load conditions.
? 1998-2013 microchip technology inc. ds30605d-page 133 pic16c63a/65b/73b/74b figure 16-15: example spi slave mode timing (cke = 1) table 16-11: example spi slave mode requirements (cke = 1) param no. symbol characteristic min typ? max units conditions 70 tssl2sch, tssl2scl ss ? to sck ? or sck ? input t cy ?? ns 71 ts c h sck input high time (slave mode) continuous 1.25t cy + 30 ? ? ns 71a single byte 40 ? ? ns (note 1) 72 ts c l sck input low time (slave mode) continuous 1.25t cy + 30 ? ? ns 72a single byte 40 ? ? ns (note 1) 73a t b 2 b last clock edge of byte1 to the 1st clock edge of byte2 1.5t cy + 40 ? ? ns (note 1) 74 ts c h 2 d i l , ts c l 2 d i l hold time of sdi data input to sck edge 100 ? ? ns 75 tdor sdo data output rise time pic16cxx ? 10 25 ns pic16lcxx 20 45 ns 76 tdof sdo data output fall time ?1025ns 77 tssh2doz ss ? to sdo output hi-impedance 10 ? 50 ns 78 ts c r sck output rise time (master mode) pic16cxx ? 10 25 ns pic16lcxx ? 20 45 ns 79 ts c f sck output fall time (master mode) ?1025ns 80 tsch2dov, tscl2dov sdo data output valid after sck edge pic16cxx ? ? 50 ns pic16lcxx ? ? 100 ns 82 tssl2dov sdo data output valid after ss ? edge pic16cxx ? ? 50 ns pic16lcxx ? ? 100 ns 83 ts c h 2 s s h , tscl2ssh ss ? after sck edge 1.5t cy + 40 ? ? ns ? data in ?typ? column is at 5 v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: specification 73a is only required if specifications 71a and 72a are used. ss sck (ckp = 0) sck (ckp = 1) sdo sdi 70 71 72 82 sdi 74 75, 76 msb bit6 - - - - - -1 lsb 77 msb in bit6 - - - -1 lsb in 80 83 note: refer to figure 16-4 for load conditions.
pic16c63a/65b/73b/74b ds30605d-page 134 ? 1998-2013 microchip technology inc. figure 16-16: i 2 c bus start/stop bits timing table 16-12: i 2 c bus start/stop bits requirements figure 16-17: i 2 c bus data timing note: refer to figure 16-4 for load conditions. 91 92 93 scl sda start condition stop condition 90 param no. sym characteristic min typ max units conditions 90* t su : sta start condition 100 khz mode 4700 ? ? ns only relevant for repeated start condition setup time 400 khz mode 600 ? ? 91* t hd : sta start condition 100 khz mode 4000 ? ? ns after this period the first clock pulse is generated hold time 400 khz mode 600 ? ? 92* t su : sto stop condition 100 khz mode 4700 ? ? ns setup time 400 khz mode 600 ? ? 93 t hd : sto stop condition 100 khz mode 4000 ? ? ns hold time 400 khz mode 600 ? ? * these parameters are characterized but not tested. note: refer to figure 16-4 for load conditions. 90 91 92 100 101 103 106 107 109 109 110 102 scl sda in sda out
? 1998-2013 microchip technology inc. ds30605d-page 135 pic16c63a/65b/73b/74b table 16-13: i 2 c bus data requirements param. no. sym characteristic min max units conditions 100* t high clock high time 100 khz mode 4.0 ? ? s device must operate at a minimum of 1.5 mhz 400 khz mode 0.6 ? ? s device must operate at a minimum of 10 mhz ssp module 1.5t cy ? 101* t low clock low time 100 khz mode 4.7 ? ? s device must operate at a minimum of 1.5 mhz 400 khz mode 1.3 ? ? s device must operate at a minimum of 10 mhz ssp module 1.5t cy ? 102* t r sda and scl rise time 100 khz mode ? 1000 ns 400 khz mode 20 + 0.1cb 300 ns cb is specified to be from 10-400 pf 103* t f sda and scl fall time 100 khz mode ? 300 ns 400 khz mode 20 + 0.1cb 300 ns cb is specified to be from 10-400 pf 90* t su : sta start condition setup time 100 khz mode 4.7 ? ? s only relevant for repeated start condition 400 khz mode 0.6 ? ? s 91* t hd : sta start condition hold time 100 khz mode 4.0 ? ? s after this period the first clock pulse is generated 400 khz mode 0.6 ? ? s 106* t hd : dat data input hold time 100 khz mode 0 ? ns 400 khz mode 0 0.9 ? s 107* t su : dat data input setup time 100 khz mode 250 ? ns (note 2) 400 khz mode 100 ? ns 92* t su : sto stop condition setup time 100 khz mode 4.7 ? ? s 400 khz mode 0.6 ? ? s 109* t aa output valid from clock 100 khz mode ? 3500 ns (note 1) 400 khz mode ? ? ns 110* t buf bus free time 100 khz mode 4.7 ? ? s time the bus must be free before a new transmission can start 400 khz mode 1.3 ? ? s cb bus capacitive loading ? 400 pf * these parameters are characterized but not tested. note 1: as a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 2: a fast mode (400 khz) i 2 c bus device can be used in a standard mode (100 khz) i 2 c bus system, but the requirement tsu:dat ?? 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t r max.+tsu;dat = 1000 + 250 = 1250 ns (according to the stan- dard mode i 2 c bus specification) before the scl line is released.
pic16c63a/65b/73b/74b ds30605d-page 136 ? 1998-2013 microchip technology inc. figure 16-18: usart sy nchronous transmission (master/slave) timing table 16-14: usart synchronous transmission requirements figure 16-19: usart synchronous receive (master/slave) timing table 16-15: usart synchrono us receive requirements note: refer to figure 16-4 for load conditions. 121 121 120 122 rc6/tx/ck rc7/rx/dt pin pin param no. sym characteristic min typ? max units conditions 120* tckh2dtv sync xmit (master & slave) clock high to data out valid pic16cxx ? ? 80 ns pic16lcxx ? ? 100 ns 121* tckrf clock out rise time and fall time (master mode) pic16cxx ? ? 45 ns pic16lcxx ? ? 50 ns 122* tdtrf data out rise time and fall time pic16cxx ? ? 45 ns pic16lcxx ? ? 50 ns * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 16-4 for load conditions. 125 126 rc6/tx/ck rc7/rx/dt pin pin param no. sym characteristic min typ? max units conditions 125* tdtv2ckl sync rcv (master & slave) data setup before ck ? (dt setup time) 15 ? ? ns 126* tckl2dtl data hold after ck ? (dt hold time) 15 ? ? ns * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested.
? 1998-2013 microchip technology inc. ds30605d-page 137 pic16c63a/65b/73b/74b table 16-16: a/d converter characteristics: pic16c73b/74b-04 (commercial, industrial, extended) pic16c73b/74b-20 (commercial, industrial, extended) pic16lc73b/74b-04 (commercial, industrial) param no. sym characteristic min typ? max units conditions a01 n r resolution pic16cxx ? ? 8 bits bit v ref = v dd = 5.12 v, v ss ? v ain ? v ref pic16lcxx ? ? 8 bits bit v ref = v dd = 2.5 v a02 e abs total absolute error ? ? < 1 lsb v ref = v dd = 5.12 v, vss ? v ain ? v ref a03 e il integral linearity error ? ? < 1 lsb v ref = v dd = 5.12 v, vss ? v ain ? v ref a04 e dl differential linearity error ? ? < 1 lsb v ref = v dd = 5.12 v, vss ? v ain ? v ref a05 e fs full scale error ? ? < 1 lsb v ref = v dd = 5.12 v, vss ? v ain ? v ref a06 e off offset error ? ? < 1 lsb v ref = v dd = 5.12 v, vss ? v ain ? v ref a10 ? monotonicity (note 3) ? guaranteed ? ? vss ? v ain ? v ref a20 v ref reference voltage 2.5v ? v dd + 0.3 v a25 v ain analog input voltage v ss - 0.3 ? v ref + 0.3 v a30 z ain recommended impedance of analog voltage source ??10.0k ? a40 i ad a/d conversion current (v dd ) pic16cxx ? 180 ? ? a average current consumption when a/d is on (note 1) pic16lcxx ? 90 ? ? a a50 i ref v ref input current (note 2) 10 ? ? ? 1000 10 ? a ? a during v ain acquisition based on differential of v hold to v ain to charge c hold , see section 12.1 during a/d conversion cycle * these parameters are characterized but not tested. ? data in ?typ? column is at 5 v, 25 ? c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: when a/d is off, it will not consume any current other than minor leakage current. the power-down current spec includes any such leakage from the a/d module. 2: v ref current is from the ra3 pin or the v dd pin, whichever is selected as a reference input. 3: the a/d conversion result never decreases with an increase in the input voltage and has no missing codes.
pic16c63a/65b/73b/74b ds30605d-page 138 ? 1998-2013 microchip technology inc. figure 16-20: a/d conversion timing table 16-17: a/d conversion requirements 131 130 132 bsf adcon0, go q4 a/d clk a/d data adres adif go sample old_data sampling stopped done new_data (t osc /2) (1) 7 6 5432 10 note 1: if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. 1 t cy 134 param no. sym characteristic min typ? max units conditions 130 t ad a/d clock period pic16cxx 1.6 ? ? ? st osc based, v ref ? 3.0 v pic16lcxx 2.0 ? ? ? st osc based, 2.5v ? v ref ? 5.5 v pic16cxx 2.0 4.0 6.0 ? s a/d rc mode pic16lcxx 3.0 6.0 9.0 ? s a/d rc mode 131 t cnv conversion time (not including s/h time) (note 1) 11 ? 11 t ad 132 t acq acquisition time 5* ? ? ? s the minimum time is the amplifier settling time. this may be used if the ?new? input voltage has not changed by more than 1 lsb (i.e., 20.0mv @ 5.12v) from the last sampled voltage (as stated on c hold ). 134 t go q4 to a/d clock start ? t osc /2 ? ? if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. 135 t swc switching from convert ? sample time 1.5 ? ? t ad * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25 ? c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: adres register may be read on the following t cy cycle. 2: see section 12.1 for minimum conditions.
? 1998-2013 microchip technology inc. ds30605d-page 139 pic16c63a/65b/73b/74b 17.0 dc and ac characteristics graphs and tables the graphs and tables provided in this section are for design guidance and are not tested nor guaranteed. in some graphs or tables the data presented is outside specified operating range (e.g., outside specified v dd range). this is for information only and devices are ensured to operate properly only within the specified range. the data presented in this section is a statistical sum- mary of data collected on units from different lots over a period of time. note: standard deviation is denoted by sigma ( ? ). ? typ or typical represents the mean of the distribution at 25c. ? max or maximum represents the mean + 3 ? over the temperature range of -40c to 85c. ? min or minimum represents the mean - 3 ? over the temperature range of -40c to 85c.
pic16c63a/65b/73b/74b ds30605d-page 140 ? 1998-2013 microchip technology inc. figure 17-1: typical i dd vs. f osc over v dd ? hs mode figure 17-2: maximum i dd vs. f osc over v dd ? hs mode 0 1 2 3 4 5 6 7 4 6 8 101214161820 f osc (mhz) i dd (ma) 5.0 v 5.5 v 4.5 v 4.0 v 3.5 v 3.0 v 2.5 v typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to 125c) minimum: mean ? 3 ? (-40c to 125c) 0 1 2 3 4 5 6 7 4 6 8 10 12 14 16 18 20 f osc (mhz) i dd (ma) 5.0 v 5.5 v 4.5 v 4.0 v 3.5 v 3.0 v 2.5 v typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to 125c) minimum: mean ? 3 ? (-40c to 125c)
? 1998-2013 microchip technology inc. ds30605d-page 141 pic16c63a/65b/73b/74b figure 17-3: typical i dd vs. f osc over v dd ? lp mode figure 17-4: maximum i dd vs. f osc over v dd ? lp mode 0 10 20 30 40 50 60 70 80 90 100 30 40 50 60 70 80 90 100 f osc (khz) i dd (a) 5.5 v 5.0 v 4.5 v 4.0 v 3.5 v 3.0 v 2.5 v typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to 125c) minimum: mean ? 3 ? (-40c to 125c) 0 20 40 60 80 100 120 140 160 30 40 50 60 70 80 90 100 f osc (khz) i dd (a) 5.5 v 5.0 v 4.5 v 4.0 v 3.5 v 3.0 v 2.5 v typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to 125c) minimum: mean ? 3 ? (-40c to 125c)
pic16c63a/65b/73b/74b ds30605d-page 142 ? 1998-2013 microchip technology inc. figure 17-5: typical i dd vs. f osc over v dd ? xt mode figure 17-6: maximum i dd vs. f osc over v dd ? xt mode 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 0.00.51.01.52.02.53.03.54.0 f osc (mhz) i dd (ma) 5.5 v 5.0 v 4.5 v 4.0 v 3.5 v 3.0 v 2.5 v typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to 125c) minimum: mean ? 3 ? (-40c to 125c) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0.00.51.01.52.02.53.03.54.0 f osc (mhz) i dd (ma) 5.5 v 5.0 v 4.5 v 4.0 v 3.5 v 3.0 v 2.5 v typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to 125c) minimum: mean ? 3 ? (-40c to 125c)
? 1998-2013 microchip technology inc. ds30605d-page 143 pic16c63a/65b/73b/74b figure 17-7: average f osc vs. v dd for various resistances ? rc mode; c = 20 pf figure 17-8: average f osc vs. v dd for various resistances ? rc mode; c = 100 pf 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 2.53.03.54.04.55.05.5 v dd (v) f osc (mhz) 3.3 k 5.1 k 10 k 100 k not recommended for operation over 4 mhz typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to 125c) minimum: mean ? 3 ? (-40c to 125c) 0.0 0.5 1.0 1.5 2.0 2.5 2.53.03.54.04.55.05.5 v dd (v) f osc (mhz) 3.3 k 5.1 k 10 k 100 k typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to 125c) minimum: mean ? 3 ? (-40c to 125c)
pic16c63a/65b/73b/74b ds30605d-page 144 ? 1998-2013 microchip technology inc. figure 17-9: average f osc vs. v dd for various resistances ? rc mode; c = 300 pf figure 17-10: v th vs. v dd over temperature ? ttl input 0 100 200 300 400 500 600 700 800 900 1,000 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) f osc (khz) 3.3 k 5.1 k 10 k 100 k typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to 125c) minimum: mean ? 3 ? (-40c to 125c) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) v th (v) max (-40c) min (125c) typ (25c) typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to 125c) minimum: mean ? 3 ? (-40c to 125c)
? 1998-2013 microchip technology inc. ds30605d-page 145 pic16c63a/65b/73b/74b figure 17-11: v il , v ih vs. v dd over temperature ? schmitt trigger input (i 2 c) figure 17-12: v il , v ih vs. v dd over temperature ? schmitt trigger input 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) v in (v) v ih typ (25c) v il typ (25c) v il max (125c) v il min (-40c) v ih max (125c) v ih min (-40c) typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to 125c) minimum: mean ? 3 ? (-40c to 125c) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) v in (v) v ih typ (25c) v il typ (25c) v il max (125c) v il min (-40c) v ih max (125c) v ih min (-40c) typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to 125c) minimum: mean ? 3 ? (-40c to 125c)
pic16c63a/65b/73b/74b ds30605d-page 146 ? 1998-2013 microchip technology inc. figure 17-13: v oh vs. i oh at v dd = 3.0 v figure 17-14: v oh vs. i oh at v dd = 5.0 v 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 5 10 15 20 25 i oh (ma) v oh (v) typical (25c) max (-40c) min (125c) typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to 125c) minimum: mean ? 3 ? (-40c to 125c) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 5 10 15 20 25 i oh (ma) v oh (v) typical (25c) max (-40c) min (125c) typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to 125c) minimum: mean ? 3 ? (-40c to 125c)
? 1998-2013 microchip technology inc. ds30605d-page 147 pic16c63a/65b/73b/74b figure 17-15: v ol vs. i ol at v dd = 3.0 v figure 17-16: v ol vs. i ol at v dd = 5.0 v 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 02468101214161820222426 i ol (-ma) v ol (v) max (125c) typ (25c) min (-40c) typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to 125c) minimum: mean ? 3 ? (-40c to 125c) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 02468101214161820222426 i ol (-ma) v ol (v) max (125c) typ (25c) min (-40c) typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to 125c) minimum: mean ? 3 ? (-40c to 125c)
pic16c63a/65b/73b/74b ds30605d-page 148 ? 1998-2013 microchip technology inc. figure 17-17: i pd vs. v dd (85c) ? sleep mode, all peripherals disabled figure 17-18: i pd vs. v dd (125c) ? sleep mode, all peripherals disabled 0 20 40 60 80 100 120 140 2.53.03.54.04.55.05.5 v dd (v) i pd (na) max 85c typ 85c max 25c max -40c typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to 125c) minimum: mean ? 3 ? (-40c to 125c) 0 200 400 600 800 1,000 1,200 1,400 2.53.03.54.04.55.05.5 v dd (v) i pd (na) max (125c) typ (125c) typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to 125c) minimum: mean ? 3 ? (-40c to 125c)
? 1998-2013 microchip technology inc. ds30605d-page 149 pic16c63a/65b/73b/74b figure 17-19: ? i bor vs. v dd over temperature (-40c to +125c) figure 17-20: ? i timer 1 vs. v dd (-10c to +70c) 0 20 40 60 80 100 120 140 160 180 200 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) ? i bor (ua) device in reset device in sleep typ (25c) typ (25c) max (125c) max (125c) indeterminant state typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to 125c) minimum: mean ? 3 ? (-40c to 125c) reset current depends on oscillator mode, frequency, and circuit. 0 20 40 60 80 100 120 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) ? i timer1 (ua) typical (25c) max (-10c to 70c) typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to 125c) minimum: mean ? 3 ? (-40c to 125c)
pic16c63a/65b/73b/74b ds30605d-page 150 ? 1998-2013 microchip technology inc. figure 17-21: ? i wdt vs. v dd (-40c to +125c) figure 17-22: wdt period vs. v dd over temperature (-40c to +125c) 0 2 4 6 8 10 12 14 16 18 20 2.53.03.54.04.55.05.5 v dd (v) ? i wdt (a) typical (25c) max (-40c to 125c) typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to 125c) minimum: mean ? 3 ? (-40c to 125c) 0 5 10 15 20 25 30 35 40 2.53.03.54.04.55.05.5 v dd (v) wdt period (ms) maximum (125c) minimum (-40c) typical (25c) typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to 125c) minimum: mean ? 3 ? (-40c to 125c)
? 1998-2013 microchip technology inc. ds30605d-page 151 pic16c63a/65b/73b/74b figure 17-23: average wdt period vs. v dd over temperature (-40c to +125c) 0 5 10 15 20 25 30 35 40 2.53.03.54.04.55.05.5 v dd (v) wdt period (ms) 125c 85c 25c -40c typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to 125c) minimum: mean ? 3 ? (-40c to 125c)
pic16c63a/65b/73b/74b ds30605d-page 152 ? 1998-2013 microchip technology inc. notes:
? 1998-2013 microchip technology inc. ds30605d-page 153 pic16c63a/65b/73b/74b 18.0 packaging information 18.1 package marking information xxxxxxxxxxxxxxxxxxxx yywwnnn xxxxxxxxxxxxxxxxxxxx example xxxxxxxxxxxxxxxxx yywwnnn 28-lead pdip (skinny dip) xxxxxxxxxxxxxxxxx example example 28-lead cerdip windowed example 0017hat pic16c73b-04/sp pic16c73b/jw 0017cat xxxxxxxxxxxxxxxxxxxx 0017saa pic16c73b-20/so 0017sbp 20i/ss025 pic16c73b- xxxxxxxxxxxxxx xxxxxxxxxxxxxx yywwnnn 28-lead soic yywwnnn xxxxxxxxxxxx xxxxxxxxxxxx 28-lead ssop legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e
pic16c63a/65b/73b/74b ds30605d-page 154 ? 1998-2013 microchip technology inc. package marking information (cont?d) xxxxxxxxxxxxxxxxxx yywwnnn 40-lead pdip xxxxxxxxxxxxxxxxxx example xxxxxxxxxxx xxxxxxxxxxx yywwnnn 40-lead cerdip windowed xxxxxxxxxxx example 44-lead tqfp xxxxxxxxxx yywwnnn xxxxxxxxxx xxxxxxxxxx example 44-lead plcc xxxxxxxxxx yywwnnn xxxxxxxxxx xxxxxxxxxx 44-lead mqfp example example xxxxxxxxxxxxxxxxxx 0017saa pic16c74b-04/p pic16c74b/jw 0017hat -20/pt 0017hat pic16c74b xxxxxxxxxx yywwnnn xxxxxxxxxx xxxxxxxxxx -20/pq 0017sat pic16c74b pic16c74b 0017sat -20/l
? 1998-2013 microchip technology inc. ds30605d-page 155 pic16c63a/65b/73b/74b 18.2 28-lead skinny plastic dual in-line (sp) ? 300 mil (pdip) 15 10 5 15 10 5 ? mold draft angle bottom 15 10 5 15 10 5 ? mold draft angle top 10.92 8.89 8.13 .430 .350 .320 eb overall row spacing 0.56 0.48 0.41 .022 .019 .016 b lower lead width 1.65 1.33 1.02 .065 .053 .040 b1 upper lead width 0.38 0.29 0.20 .015 .012 .008 c lead thickness 3.43 3.30 3.18 .135 .130 .125 l tip to seating plane 35.18 34.67 34.16 1.385 1.365 1.345 d overall length 7.49 7.24 6.99 .295 .285 .275 e1 molded package width 8.26 7.87 7.62 .325 .310 .300 e shoulder to shoulder width 0.38 .015 a1 base to seating plane 3.43 3.30 3.18 .135 .130 .125 a2 molded package thickness 4.06 3.81 3.56 .160 .150 .140 a top to seating plane 2.54 .100 p pitch 28 28 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d n e1 c eb ? e ? p l a2 b b1 a a1 notes: jedec equivalent: mo-095 drawing no. c04-070 * controlling parameter dimension d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. significant characteristic note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
pic16c63a/65b/73b/74b ds30605d-page 156 ? 1998-2013 microchip technology inc. 18.3 28-lead ceramic dual in-line with window (jw) ? 300 mil (cerdip) 3.30 3.56 3.81 7.87 7.62 7.37 .310 .300 .290 w2 window length .150 .140 .130 w1 window width 10.80 9.78 8.76 .425 .385 .345 eb overall row spacing 0.53 0.47 0.41 .021 .019 .016 b lower lead width 1.65 1.46 1.27 .065 .058 .050 b1 upper lead width 0.30 0.25 0.20 .012 .010 .008 c lead thickness 3.68 3.56 3.43 .145 .140 .135 l tip to seating plane 37.72 37.02 36.32 1.485 1.458 1.430 d overall length 7.49 7.37 7.24 .295 .290 .285 e1 ceramic pkg. width 8.26 7.94 7.62 .325 .313 .300 e shoulder to shoulder width 0.76 0.57 0.38 .030 .023 .015 a1 standoff 4.19 4.06 3.94 .165 .160 .155 a2 ceramic package height 4.95 4.64 4.32 .195 .183 .170 a top to seating plane 2.54 .100 p pitch 28 28 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d n w2 w1 e1 e eb p a2 l b1 b a1 a * controlling parameter c significant characteristic jedec equivalent: mo-058 drawing no. c04-080 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 1998-2013 microchip technology inc. ds30605d-page 157 pic16c63a/65b/73b/74b 18.4 28-lead plastic small outline (so) ? wide, 300 mil (soic) foot angle top ? 048048 15 12 0 15 12 0 ? mold draft angle bottom 15 12 0 15 12 0 ? mold draft angle top 0.51 0.42 0.36 .020 .017 .014 b lead width 0.33 0.28 0.23 .013 .011 .009 c lead thickness 1.27 0.84 0.41 .050 .033 .016 l foot length 0.74 0.50 0.25 .029 .020 .010 h chamfer distance 18.08 17.87 17.65 .712 .704 .695 d overall length 7.59 7.49 7.32 .299 .295 .288 e1 molded package width 10.67 10.34 10.01 .420 .407 .394 e overall width 0.30 0.20 0.10 .012 .008 .004 a1 standoff 2.39 2.31 2.24 .094 .091 .088 a2 molded package thickness 2.64 2.50 2.36 .104 .099 .093 a overall height 1.27 .050 p pitch 28 28 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d p n b e e1 l c ? 45 ? h ? a2 ? a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-013 drawing no. c04-052 significant characteristic note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
pic16c63a/65b/73b/74b ds30605d-page 158 ? 1998-2013 microchip technology inc. 18.5 28-lead plastic shrink small outline (ss) ? 209 mil, 5.30 mm (ssop) * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-150 drawing no. c04-073 10 5 0 10 5 0 mold draft angle bottom 10 5 0 10 5 0 ? mold draft angle top 0.38 0.32 0.25 .015 .013 .010 b lead width 203.20 101.60 0.00 8 4 0 ? foot angle 0.25 0.18 0.10 .010 .007 .004 c lead thickness 0.94 0.75 0.56 .037 .030 .022 l foot length 10.34 10.20 10.06 .407 .402 .396 d overall length 5.38 5.25 5.11 .212 .207 .201 e1 molded package width 8.10 7.85 7.59 .319 .309 .299 e overall width 0.25 0.15 0.05 .010 .006 .002 a1 standoff 1.83 1.73 1.63 .072 .068 .064 a2 molded package thickness 1.98 1.85 1.73 .078 .073 .068 a overall height 0.65 .026 p pitch 28 28 n number of pins max nom min max nom min dimension limits millimeters* inches units 2 1 d p n b e1 e l ? c ? ? a2 a1 a ? significant characteristic note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 1998-2013 microchip technology inc. ds30605d-page 159 pic16c63a/65b/73b/74b 18.6 40-lead plastic dual in-line (p) ? 600 mil (pdip) 15 10 5 15 10 5 ? mold draft angle bottom 15 10 5 15 10 5 ? mold draft angle top 17.27 16.51 15.75 .680 .650 .620 eb overall row spacing 0.56 0.46 0.36 .022 .018 .014 b lower lead width 1.78 1.27 0.76 .070 .050 .030 b1 upper lead width 0.38 0.29 0.20 .015 .012 .008 c lead thickness 3.43 3.30 3.05 .135 .130 .120 l tip to seating plane 52.45 52.26 51.94 2.065 2.058 2.045 d overall length 14.22 13.84 13.46 .560 .545 .530 e1 molded package width 15.88 15.24 15.11 .625 .600 .595 e shoulder to shoulder width 0.38 .015 a1 base to seating plane 4.06 3.81 3.56 .160 .150 .140 a2 molded package thickness 4.83 4.45 4.06 .190 .175 .160 a top to seating plane 2.54 .100 p pitch 40 40 n number of pins max nom min max nom min dimension limits millimeters inches* units a2 1 2 d n e1 c ? eb e ? p l b b1 a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: mo-011 drawing no. c04-016 significant characteristic note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
pic16c63a/65b/73b/74b ds30605d-page 160 ? 1998-2013 microchip technology inc. 18.7 40-lead ceramic dual in-line with window (jw) ? 600 mil (cerdip) 9.14 8.89 8.64 .360 .350 .340 w window diameter 18.03 16.76 15.49 .710 .660 .610 eb overall row spacing 0.58 0.51 0.41 .023 .020 .016 b1 lower lead width 1.40 1.33 1.27 .055 .053 .050 b upper lead width 0.36 0.28 0.20 .014 .011 .008 c lead thickness 3.68 3.56 3.43 .145 .140 .135 l tip to seating plane 52.32 52.07 51.82 2.060 2.050 2.040 d overall length 13.36 13.21 13.06 .526 .520 .514 e1 ceramic pkg. width 15.88 15.24 15.11 .625 .600 .595 e shoulder to shoulder width 1.52 1.14 0.76 .060 .045 .030 a1 standoff 4.19 4.06 3.94 .165 .160 .155 a2 ceramic package height 5.72 5.21 4.70 .225 .205 .185 a top to seating plane 2.54 .100 p pitch 40 40 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d n c eb e p l b1 b a2 * controlling parameter significant characteristic jedec equivalent: mo-103 drawing no. c04-014 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 1998-2013 microchip technology inc. ds30605d-page 161 pic16c63a/65b/73b/74b 18.8 44-lead plastic thin quad flatpack (pt) 10x10x1 mm body, 1.0/0.10 mm lead form (tqfp) * controlling parameter notes: dimensions d1 and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-026 drawing no. c04-076 1.14 0.89 0.64 .045 .035 .025 ch pin 1 corner chamfer 1.00 .039 (f) footprint (reference) (f) a a1 a2 ? e e1 #leads=n1 p b d1 d n 1 2 ? c ? l units inches millimeters* dimension limits min nom max min nom max number of pins n 44 44 pitch p .031 0.80 overall height a .039 .043 .047 1.00 1.10 1.20 molded package thickness a2 .037 .039 .041 0.95 1.00 1.05 standoff a1 .002 .004 .006 0.05 0.10 0.15 foot length l .018 .024 .030 0.45 0.60 0.75 foot angle ? 03.5 7 03.5 7 overall width e .463 .472 .482 11.75 12.00 12.25 overall length d .463 .472 .482 11.75 12.00 12.25 molded package width e1 .390 .394 .398 9.90 10.00 10.10 molded package length d1 .390 .394 .398 9.90 10.00 10.10 pins per side n1 11 11 lead thickness c .004 .006 .008 0.09 0.15 0.20 lead width b .012 .015 .017 0.30 0.38 0.44 mold draft angle top ? 51015 51015 mold draft angle bottom ? 51015 51015 ch x 45 ? significant characteristic note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
pic16c63a/65b/73b/74b ds30605d-page 162 ? 1998-2013 microchip technology inc. 18.9 44-lead plastic metric quad flatpack (pq) 10x10x2 mm body, 1.6/0.15 mm lead form (mqfp) * controlling parameter notes: dimensions d1 and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-022 drawing no. c04-071 b d1 e ch 15 10 5 15 10 5 ? mold draft angle bottom 15 10 5 15 10 5 ? mold draft angle top 0.45 0.38 0.30 .018 .015 .012 lead width 0.23 0.18 0.13 .009 .007 .005 c lead thickness 11 11 n1 pins per side 10.10 10.00 9.90 .398 .394 .390 molded package length 10.10 10.00 9.90 .398 .394 .390 e1 molded package width 13.45 13.20 12.95 .530 .520 .510 d overall length 13.45 13.20 12.95 .530 .520 .510 overall width 7 3.5 0 7 3.5 0 ? foot angle 1.03 0.88 0.73 .041 .035 .029 l foot length 0.25 0.15 0.05 .010 .006 .002 a1 standoff 2.10 2.03 1.95 .083 .080 .077 a2 molded package thickness 2.35 .093 a overall height 0.80 .031 p pitch 44 44 n number of pins max nom min max nom min dimension limits millimeters* inches units 2 1 n d1 d b p e e1 #leads=n1 c ? ? ? a2 a ch x 45 ? l pin 1 corner chamfer footprint (reference) (f) .063 1.60 .025 .035 .045 0.64 0.89 1.14 (f) a1 .079 .086 2.00 2.18 significant characteristic note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 1998-2013 microchip technology inc. ds30605d-page 163 pic16c63a/65b/73b/74b 18.10 44-lead plastic leaded chip carrier (l) ? square (plcc) ch2 x 45 ? ch1 x 45 ? 10 5 0 10 5 0 ? mold draft angle bottom 10 5 0 10 5 0 ? mold draft angle top 0.53 0.51 0.33 .021 .020 .013 b 0.81 0.74 0.66 .032 .029 .026 b1 upper lead width 0.33 0.27 0.20 .013 .011 .008 c lead thickness 11 11 n1 pins per side 16.00 15.75 14.99 .630 .620 .590 d2 footprint length 16.00 15.75 14.99 .630 .620 .590 e2 footprint width 16.66 16.59 16.51 .656 .653 .650 d1 molded package length 16.66 16.59 16.51 .656 .653 .650 e1 molded package width 17.65 17.53 17.40 .695 .690 .685 d overall length 17.65 17.53 17.40 .695 .690 .685 e overall width 0.25 0.13 0.00 .010 .005 .000 ch2 corner chamfer (others) 1.27 1.14 1.02 .050 .045 .040 ch1 corner chamfer 1 0.86 0.74 0.61 .034 .029 .024 a3 side 1 chamfer height 0.51 .020 a1 standoff a2 molded package thickness 4.57 4.39 4.19 .180 .173 .165 a overall height 1.27 .050 p pitch 44 44 n number of pins max nom min max nom min dimension limits millimeters inches* units ? a2 c e2 2 d d1 n #leads=n1 e e1 1 ? p a3 a 35 ? b1 b d2 a1 .145 .153 .160 3.68 3.87 4.06 .028 .035 0.71 0.89 lower lead width * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: mo-047 drawing no. c04-048 significant characteristic note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
pic16c63a/65b/73b/74b ds30605d-page 164 ? 1998-2013 microchip technology inc. notes:
? 1998-2013 microchip technology inc. ds30605d-page 165 pic16c63a/65b/73b/74b appendix a: revision history appendix b: device differences the differences between the devices in this data sheet are listed in table b-1. version date revision description a 7/98 this is a new data sheet. however, the devices described in this data sheet are the upgrades to the devices found in the pic16c6x data sheet , ds30234, and the pic16c7x data sheet , ds30390. b 1/99 corrections to version a data sheet for technical accuracy. added data: ? operation of the smp and cke bits of the sspstat register in i 2 c mode have been specified ? frequency vs. v dd graphs for device operating area (in electrical specifications) ? formula for calculating a/d acquisition time, t acq (in the a/d section) ? brief description of instructions removed data (see picmicro tm mid-range mcu family reference manual, ds33023, for additional data): ? usart baud rate tables (formulas for calculating baud rate remain) c 12/00 ? minor changes to text to clarify content ? revised some dc specifications ? included characteristic charts and graphs d 01/13 ? added a note to every package drawing. table b-1: device differences difference pic16c63a pic16c65b pic16c73b pic16c74b a/d no no 5 channels, 8 bits 8 channels, 8 bits parallel slave port no yes no yes packages 28-pin pdip, 28-pin windowed cerdip, 28-pin soic, 28-pin ssop 40-pin pdip, 40-pin windowed cerdip, 44-pin tqfp, 44-pin mqfp, 44-pin plcc 28-pin pdip, 28-pin windowed cerdip, 28-pin soic, 28-pin ssop 40-pin pdip, 40-pin windowed cerdip, 44-pin tqfp, 44-pin mqfp, 44-pin plcc
pic16c63a/65b/73b/74b ds30605d-page 166 ? 1998-2013 microchip technology inc. appendix c: device migrations - pic16c63/65a/73a/74a ? pic16c63a/65b/73b/74b this document is intended to describe the functional differences and the electrical specification differences that are present when migrating from one device to the next. table c-1 shows functional differences, while table c-2 shows electrical and timing differences. table c-1: functional differences note: even though compatible devices are specified to be tested to the same electrical specification, the device characteristics may be different from each other (due to process differences). for systems that were designed to the device specifications, these process differences should not cause any issues in the appli- cation. for systems that did not tightly meet the electrical specifications, the process differences may cause the device to behave differently in the application. note: while there are no functional or electrical changes to the device oscillator specifications, the user should verify that the device oscillator starts and performs as expected. adjusting the loading capacitor values and/or the oscillator mode may be required. no. module differences from pic16c63/65a/73a/74a h/w s/w prog. 1 ccp ccp special event trigger clears timer1. ? ? ? 2 compare mode drives pin correctly. ? ? ? 3 timers writing to tmr1l does not affect tmr1h. ? ? ? 4 wdt/tmr0 prescaler assignment changes do not affect tmr0 count. ? ? ? 5 ssp tmr2 spi clock synchronized to start of spi transmission. ? ? ? 6 can now transmit multiple words in spi mode. ? ? ? 7 supports all four spi modes. (now uses ssp vs. bssp module.) see ssp module in the pic ? mid-range mcu family reference manual (ds33023). ? ? ? 8i 2 c no longer generates ack pulses when module is enabled. ? ? ? 9 usart async receive errors due to brgh setting corrected. ? ? ? 10 a/d v ref = v dd when all inputs are configured as digital. this allows conversion of digital inputs. (a/d on pic16c73x/74x only.) ? ? ? h/w - issues may exist with regard to the application circuits. s/w - issues may exist with regard to the user program. prog. - issues may exist when writing the program to the controller.
? 1998-2013 microchip technology inc. ds30605d-page 167 pic16c63a/65b/73b/74b table c-2: specification differences param no. symbol characteristic pic16c63/65a/73a/74a pic16c63a/65b/73b/74b unit min typ? max min typ? max core d001 d001a v dd supply voltage 4.0 ? ? ? 6.0 ? 4.0 v bor (1) ? ? 5.5 5.5 v v d005 b vdd brown-out reset voltage 3.7 4.0 4.3 3.65 ? 4.35 v d150* v od open-drain high voltage on ra4 ??14.0 - ? 8.5 v a/d converter a20 v ref reference voltage 3.0 ? v dd + 0.3 2.5 ?v dd + 0.3 v 131 t cnv conversion time (note 2) (not including s/h time) ?9.5 (note 3) ? 11 (note 4) ? 11 (note 4) t ad ssp in spi mode 71 tsch sck input high time (slave mode) continuous t cy +20 ? ? 1.25t cy + 30 ??ns 71a single byte 40 ??ns 72 tscl sck input low time (slave mode) continuous t cy +20 ? ? 1.25t cy + 30 ??ns 72a single byte 40 ??ns 73 tdiv2sch tdiv2scl setup time of sdi data input to sck edge 50 ? ? 100 ??ns 73a (note 5) t b 2 b last clock edge of byte1 to the 1st clock edge of byte2 ?? ? 1.5t cy + 40 ??ns 74 tsch2dil tscl2dil hold time of sdi data input to sck edge 50 ? ? 100 ??ns 75 tdor sdo data output rise time pic16cxx ? 10 25 ? 10 25 ns pic16lcxx ? 20 45 ns 78 tscr sck output rise time (master mode) pic16cxx ? 10 25 ? 10 25 ns pic16lcxx ? 20 45 ns 80 tsch2dov tscl2dov sdo data output valid after sck edge pic16cxx ? ? 50 ? ? 50 ns pic16lcxx ? ? 100 ns 83 tsch2ssh ts c l 2 s s h ss ? after sck edge ? ? 50 1.5t cy + 40 ??ns ? data in ?typ? column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: when bor is enabled, the device will operate until v dd drops below v bor . 2: adres register may be read on the following t cy cycle. 3: this is the time that the actual conversion requires. 4: this is the time from when the go/done bit is set, to when the conversion result appears in adres. 5: specification 73a is only required if specifications 71a and 72a are used.
pic16c63a/65b/73b/74b ds30605d-page 168 ? 1998-2013 microchip technology inc. appendix d: migration from baseline to mid-range devices this section discusses how to migrate from a baseline device (i.e., pic16c5x) to a mid-range device (i.e., pic16cxxx). the following are the list of modifications over the pic16c5x microcontroller family: 1. instruction word length is increased to 14-bits. this allows larger page sizes, both in program memory (2 k now as opposed to 512 before) and register file (128 bytes now versus 32 bytes before). 2. a pc high latch register (pclath) is added to handle program memory paging. bits pa2, pa1 and pa0 are removed from status register. 3. data memory paging is redefined slightly. status register is modified. 4. four new instructions have been added: return, retfie, addlw and sublw . two instructions, tris and option, are being phased out, although they are kept for compati- bility with pic16c5x. 5. option and tris registers are made address- able. 6. interrupt capability is added. interrupt vector is at 0004h. 7. stack size is increased to 8-deep. 8. reset vector is changed to 0000h. 9. reset of all registers is revisited. five different reset (and wake-up) types are recognized. registers are reset differently. 10. wake up from sleep through interrupt is added. 11. two separate timers, oscillator start-up timer (ost) and power-up timer (pwrt) are included for more reliable power-up. these tim- ers are invoked selectively to avoid unneces- sary delays on power-up and wake-up. 12. portb has weak pull-ups and interrupt-on-change feature. 13. t0cki pin is also a port pin (ra4) now. 14. fsr is made a full 8-bit register. 15. ?in-circuit serial programming? (icsp) is made possible. the user can program pic16cxx devices using only five pins: v dd , v ss , mclr /v pp , rb6 (clock) and rb7 (data in/out). 16. pcon status register is added with a power-on reset status bit (por ). 17. code protection scheme is enhanced, such that portions of the program memory can be pro- tected, while the remainder is unprotected. 18. brown-out protection circuitry has been added. controlled by configuration word bit boden. brown-out reset ensures the device is placed in a reset condition if v dd dips below a fixed setpoint. to convert code written for pic16c5x to pic16cxx, the user should take the following steps: 1. remove any program memory page select operations (pa2, pa1, pa0 bits) for call , goto . 2. revisit any computed jump operations (write to pc or add to pc, etc.) to make sure page bits are set properly under the new scheme. 3. eliminate any data memory page switching. redefine data variables to reallocate them. 4. verify all writes to status, option and fsr registers since these have changed. 5. change reset vector to 0000h.
? 1998-2013 microchip technology inc. ds30605d-page 169 pic16c63a/65b/73b/74b index a a/d adcon0 register....................................................... 79 adcon1 register....................................................... 80 analog input model block diagram............................. 82 analog-to-digital converter......................................... 79 block diagram............................................................. 81 configuring analog port pins...................................... 83 configuring the interrupt ............................................. 81 configuring the module............................................... 81 conversion clock........................................................ 83 conversions ................................................................ 83 converter characteristics ......................................... 137 effects of a reset ..................................................... 83 faster conversion - lower resolution trade-off ........ 83 internal sampling switch (rss) impedance ................ 82 operation during sleep ............................................ 83 sampling requirements.............................................. 82 source impedance...................................................... 82 timing diagram......................................................... 138 using the ccp trigger ................................................ 83 absolute maximum ratings .............................................. 113 ack ............................................................................... 60, 62 adres register ........................................................... 17, 79 application notes an552 (implementing wake-up on key strokes using pic16cxxx)..................................................... 31 an556 (table reading using pic16cxx) .................. 26 an578 (use of the ssp module in the i 2 c multi-master environment).......................................... 55 an607, (power-up trouble shooting) ......................... 89 architecture overview ....................................................................... 9 assembler mpasm ? assembler ................................................. 107 b baud rate formula ............................................................. 67 bf ................................................................................. 56, 60 block diagrams a/d .............................................................................. 81 analog input model ..................................................... 82 capture ....................................................................... 51 compare ..................................................................... 52 i 2 c mode..................................................................... 60 on-chip reset circuit ................................................. 88 pic16c74 ................................................................... 10 pic16c74a ................................................................. 10 pic16c77 ................................................................... 10 portc ....................................................................... 33 portd (in i/o port mode).......................................... 34 portd and porte as a parallel slave port............. 37 porte (in i/o port mode).......................................... 35 pwm ........................................................................... 52 ra4/t0cki pin............................................................ 29 rb3:rb0 port pins ..................................................... 31 rb7:rb4 port pins ..................................................... 31 ssp in i 2 c mode......................................................... 60 ssp in spi mode ........................................................ 55 timer0/wdt prescaler................................................ 39 timer2 ......................................................................... 47 usart receive.......................................................... 70 usart transmit ......................................................... 68 watchdog timer .......................................................... 96 bor bit ......................................................................... 25, 89 brgh bit ............................................................................ 67 brown-out reset (bor) timing diagram ........................................................ 126 buffer full status bit, bf..................................................... 56 c c bit .................................................................................... 19 capture/compare/pwm capture block diagram .................................................... 51 ccp1con register............................................ 50 ccp1if............................................................... 51 mode .................................................................. 51 prescaler ............................................................ 51 ccp timer resources................................................ 49 compare block diagram .................................................... 52 mode .................................................................. 52 software interrupt mode ..................................... 52 special event trigger ......................................... 52 special trigger output of ccp1 ......................... 52 special trigger output of ccp2 ......................... 52 interaction of two ccp modules ................................ 49 section........................................................................ 49 special event trigger and a/d conversions............... 52 capture/compare/pwm (ccp) pwm block diagram .................................................. 52 pwm mode................................................................. 52 pwm, example frequencies/resolutions .................. 53 timing diagram ........................................................ 128 ccp2ie bit .......................................................................... 24 ccp2if bit .......................................................................... 24 ccpr1h register......................................................... 17, 49 ccpr1l register ............................................................... 49 ccpr2h register............................................................... 17 ccpr2l register ............................................................... 17 ccpxm0 bit......................................................................... 50 ccpxm1 bit......................................................................... 50 ccpxm2 bit......................................................................... 50 ccpxm3 bit......................................................................... 50 ccpxx bit ........................................................................... 50 ccpxy bit ........................................................................... 50 cke .................................................................................... 56 ckp .................................................................................... 57 clock polarity select bit, ckp............................................. 57 clocking scheme................................................................ 14 code examples call of a subroutine in page 1 from page 0 ............... 26 indirect addressing ..................................................... 27 initializing porta....................................................... 29 code protection ............................................................ 85, 98 computed goto................................................................ 26 configuration bits ............................................................... 85 cren bit............................................................................. 66 cs pin................................................................................. 37
pic16c63a/65b/73b/74b ds30605d-page 170 ? 1998-2013 microchip technology inc. d d/a ...................................................................................... 56 data memory register file map ........................................................ 16 data/address bit, d/a .......................................................... 56 dc bit .................................................................................. 19 development support ........................................................... 5 device differences ............................................................ 165 direct addressing................................................................ 27 e electrical characteristics................................................... 113 errata .................................................................................... 3 f ferr bit.............................................................................. 66 fsr register........................................................... 17, 18, 27 g general description .............................................................. 5 gie bit ................................................................................. 93 i i/o ports porta ........................................................................ 29 portb........................................................................ 31 portc........................................................................ 33 portd.................................................................. 34, 37 porte........................................................................ 35 section ........................................................................ 29 i 2 c addressing .................................................................. 61 block diagram............................................................. 60 i 2 c operation .............................................................. 60 master mode ............................................................... 64 mode ........................................................................... 60 mode selection ........................................................... 60 multi-master mode ...................................................... 64 reception .................................................................... 62 reception timing diagram.......................................... 62 scl and sda pins ...................................................... 60 slave mode ................................................................. 60 transmission............................................................... 63 i 2 c (ssp module) timing diagram, data ............................................... 134 timing diagram, start/stop bits.......................... 134 in-circuit serial programming ....................................... 85, 98 indf register ......................................................... 17, 18, 27 indirect addressing ............................................................. 27 instruction cycle.................................................................. 14 instruction flow/pipelining .................................................. 14 instruction format ............................................................... 99 instruction set addlw ..................................................................... 101 addwf ..................................................................... 101 andlw ..................................................................... 101 andwf ..................................................................... 101 bcf ........................................................................... 101 bsf ........................................................................... 101 btfsc ...................................................................... 102 btfss ...................................................................... 102 call ......................................................................... 102 clrf......................................................................... 102 clrw........................................................................ 102 clrwdt................................................................... 102 comf ....................................................................... 103 decf ........................................................................ 103 decfsz ................................................................... 103 goto ....................................................................... 103 incf ......................................................................... 103 incfsz..................................................................... 103 iorlw ...................................................................... 104 iorwf...................................................................... 104 movf ....................................................................... 104 movlw .................................................................... 104 movwf .................................................................... 104 nop .......................................................................... 104 retfie ..................................................................... 105 retlw ..................................................................... 105 return................................................................... 105 rlf ........................................................................... 105 rrf .......................................................................... 105 sleep ...................................................................... 105 sublw ..................................................................... 106 subwf..................................................................... 106 swapf ..................................................................... 106 xorlw..................................................................... 106 xorwf .................................................................... 106 section........................................................................ 99 summary table......................................................... 100 int interrupt........................................................................ 94 intcon register................................................................ 21 intedg bit ................................................................... 20, 94 internal sampling switch (rss) impedance........................ 82 interrupts............................................................................. 85 portb change.......................................................... 94 rb7:rb4 port change................................................ 31 section........................................................................ 93 tmr0 .......................................................................... 94 irp bit ................................................................................. 19 k k ee l oq evaluation and programming tools .................... 110 l loading of pc ..................................................................... 26 m mclr ............................................................................ 87, 90 memory data memory .............................................................. 15 program memory ........................................................ 15 program memory maps pic16c73 ........................................................... 15 pic16c73a......................................................... 15 pic16c74 ........................................................... 15 pic16c74a......................................................... 15 register file maps pic16c73 ........................................................... 16 pic16c73a......................................................... 16 pic16c74 ........................................................... 16 pic16c74a......................................................... 16 pic16c76 ........................................................... 16 pic16c77 ........................................................... 16 mplab ? integrated development environment software ...................................................... 107
? 1998-2013 microchip technology inc. ds30605d-page 171 pic16c63a/65b/73b/74b o oerr bit............................................................................. 66 opcode ............................................................................ 99 option register................................................................ 20 osc selection .................................................................... 85 oscillator hs ......................................................................... 86, 90 lp.......................................................................... 86, 90 rc............................................................................... 86 xt ......................................................................... 86, 90 oscillator configurations ..................................................... 86 output of tmr2 .................................................................. 47 p p.......................................................................................... 56 packaging ......................................................................... 153 paging, program memory ................................................... 26 parallel slave port ........................................................ 34, 37 parallel slave port (psp) timing diagram......................................................... 129 pcfg0 bit ........................................................................... 80 pcfg1 bit ........................................................................... 80 pcfg2 bit ........................................................................... 80 pcl register........................................................... 17, 18, 26 pclath .............................................................................. 91 pclath register ................................................... 17, 18, 26 pcon register ............................................................. 25, 89 pd bit ............................................................................ 19, 87 picdem tm 1 low cost pic mcu demonstration board ........................................................ 109 picdem tm 2 low cost pic16cxx demonstration board ........................................................ 109 picdem tm 3 low cost pic16cxxx demonstration board ........................................................ 110 picstart ? plus entry level development system ........................................................ 109 pie1 register...................................................................... 22 pie2 register...................................................................... 24 pin functions mclr /v pp ............................................................. 11, 12 osc1/clkin......................................................... 11, 12 osc2/clkout..................................................... 11, 12 ra0/an0 ............................................................... 11, 12 ra1/an1 ............................................................... 11, 12 ra2/an2 ............................................................... 11, 12 ra3/an3/v ref ...................................................... 11, 12 ra4/t0cki............................................................ 11, 12 ra5/an4/ss ......................................................... 11, 12 rb0/int ................................................................ 11, 12 rb1 ....................................................................... 11, 12 rb2 ....................................................................... 11, 12 rb3 ....................................................................... 11, 12 rb4 ....................................................................... 11, 12 rb5 ....................................................................... 11, 12 rb6 ....................................................................... 11, 12 rb7 ....................................................................... 11, 12 rc0/t1oso/t1cki .............................................. 11, 13 rc1/t1osi/ccp2................................................. 11, 13 rc2/ccp1 ............................................................ 11, 13 rc3/sck/scl ...................................................... 11, 13 rc4/sdi/sda ....................................................... 11, 13 rc5/sdo .............................................................. 11, 13 rc6/tx/ck ............................................... 11, 13, 65?76 rc7/rx/dt ............................................... 11, 13, 65?76 rd0/psp0................................................................... 13 rd1/psp1 .................................................................. 13 rd2/psp2 .................................................................. 13 rd3/psp3 .................................................................. 13 rd4/psp4 .................................................................. 13 rd5/psp5 .................................................................. 13 rd6/psp6 .................................................................. 13 rd7/psp7 .................................................................. 13 re0/rd /an5 .............................................................. 13 re1/wr /an6.............................................................. 13 re2/cs /an7............................................................... 13 v dd ........................................................................11, 13 v ss ........................................................................11, 13 pinout descriptions pic16c73 ................................................................... 11 pic16c73a................................................................. 11 pic16c74 ................................................................... 12 pic16c74a................................................................. 12 pic16c76 ................................................................... 11 pic16c77 ................................................................... 12 pir1 register ..................................................................... 23 pir2 register ..................................................................... 24 pop .................................................................................... 26 por .................................................................................... 89 oscillator start-up timer (ost) ............................ 85, 89 power control register (pcon)................................. 89 power-on reset (por)................................... 85, 89, 91 power-up timer (pwrt) ............................................ 85 power-up-timer (pwrt) ........................................... 89 to ............................................................................... 87 por bit ......................................................................... 25, 89 port rb interrupt................................................................. 94 porta ............................................................................... 91 porta register ........................................................... 17, 29 portb ............................................................................... 91 portb register ........................................................... 17, 31 portc ............................................................................... 91 portc register........................................................... 17, 33 portd ............................................................................... 91 portd register........................................................... 17, 34 porte ............................................................................... 91 porte register ........................................................... 17, 35 power-down mode (sleep)............................................... 97 power-on reset (por) timing diagram ........................................................ 126 pr2 register ................................................................ 18, 47 pro mate ? ii universal programmer ............................. 109 product identification system ........................................... 177 program memory paging ........................................................................ 26 program memory maps pic16c73 ................................................................... 15 pic16c73a................................................................. 15 pic16c74 ................................................................... 15 pic16c74a................................................................. 15 program verification ........................................................... 98 ps0 bit ................................................................................ 20 ps1 bit ................................................................................ 20 ps2 bit ................................................................................ 20 psa bit................................................................................ 20 pspmode bit ......................................................... 34, 35, 37 push.................................................................................. 26
pic16c63a/65b/73b/74b ds30605d-page 172 ? 1998-2013 microchip technology inc. r r/w ..................................................................................... 56 r/w bit .................................................................... 61, 62, 63 rbif bit ......................................................................... 31, 94 rbpu bit ............................................................................. 20 rc oscillator ................................................................. 87, 90 rcsta register.................................................................. 66 rd pin ................................................................................. 37 read/write bit information, r/w ......................................... 56 receive overflow indicator bit, sspov .............................. 57 register file ........................................................................ 15 register file map ................................................................ 16 registers maps pic16c73 ........................................................... 16 pic16c73a ......................................................... 16 pic16c74 ........................................................... 16 pic16c74a ......................................................... 16 reset conditions ...................................................... 90 sspstat .................................................................... 56 summary..................................................................... 17 reset .......................................................................... 85, 87 timing diagram......................................................... 126 reset conditions for special registers ............................ 90 revision history ................................................................ 165 rp0 bit .......................................................................... 15, 19 rp1 bit ................................................................................ 19 rx9 bit ................................................................................ 66 rx9d bit.............................................................................. 66 s s.......................................................................................... 56 scl ..................................................................................... 60 serial communication interface (sci) module, see usart services one-time-programmable (otp)................................... 7 quick-turnaround-production (qtp) ............................ 7 serialized quick-turnaround production (sqtp) .......................................................................... 7 slave mode scl ............................................................................. 60 sda............................................................................. 60 sleep........................................................................... 85, 87 smp .................................................................................... 56 software simulator (mplab-sim)..................................... 108 spbrg register ................................................................. 18 special features of the cpu............................................... 85 special function registers pic16c73 ................................................................... 17 pic16c73a ................................................................. 17 pic16c74 ................................................................... 17 pic16c74a ................................................................. 17 special function registers, section ................................... 16 spen bit.............................................................................. 66 spi block diagram............................................................. 55 master mode timing ................................................... 58 serial clock................................................................. 55 serial data in .............................................................. 55 serial data out............................................................ 55 slave mode timing ..................................................... 59 slave mode timing diagram....................................... 58 slave select ................................................................ 55 sspcon ..................................................................... 57 sspstat.................................................................... 56 spi clock edge select bit, cke ......................................... 56 spi data input sample phase select bit, smp .................. 56 sren bit ............................................................................. 66 ssp module overview ........................................................ 55 section........................................................................ 55 sspcon .................................................................... 57 sspstat.................................................................... 56 sspadd register............................................................... 18 sspbuf register ............................................................... 17 sspcon............................................................................. 57 sspcon register .............................................................. 17 sspen................................................................................ 57 sspm3:sspm0 .................................................................. 57 sspov ......................................................................... 57, 60 sspstat register ....................................................... 18, 56 stack................................................................................... 26 overflows.................................................................... 26 underflow ................................................................... 26 start bit, s....................................................................... 56 status register ............................................................... 19 stop bit, p......................................................................... 56 synchronous serial port enable bit, sspen...................... 57 synchronous serial port mode select bits, sspm3:sspm0 .................................................................. 57 synchronous serial port module ........................................ 55 synchronous serial port status register ........................... 56 t t0cs bit.............................................................................. 20 t1ckps0 bit ....................................................................... 43 t1ckps1 bit ....................................................................... 43 t1con register ................................................................. 43 t1oscen bit ...................................................................... 43 t1sync bit......................................................................... 43 t2ckps0 bit ....................................................................... 47 t2ckps1 bit ....................................................................... 47 t2con register ................................................................. 47 t ad ...................................................................................... 83 timer0 rtcc.......................................................................... 91 timing diagram ........................................................ 127 timer1 timing diagram ........................................................ 127 timers timer0 external clock .................................................... 40 interrupt .............................................................. 39 prescaler ............................................................ 40 prescaler block diagram .................................... 39 section................................................................ 39 t0cki ................................................................. 40 t0if .................................................................... 94 tmr0 interrupt ................................................... 94 timer1 asynchronous counter mode ............................. 45 capacitor selection ............................................ 45 operation in timer mode .................................... 44 oscillator............................................................. 45 prescaler ............................................................ 45 resetting of timer1 registers ............................ 45 resetting timer1 using a ccp trigger output .................................................... 45 synchronized counter mode .............................. 44 t1con ............................................................... 43
? 1998-2013 microchip technology inc. ds30605d-page 173 pic16c63a/65b/73b/74b tmr1h ............................................................... 45 tmr1l ................................................................ 45 timer2 block diagram .................................................... 47 module ................................................................ 47 postscaler ........................................................... 47 prescaler............................................................. 47 t2con................................................................ 47 timing diagrams i 2 c reception (7-bit address) ..................................... 62 spi master mode ........................................................ 58 spi slave mode (cke = 1) ......................................... 59 spi slave mode timing (cke = 0).............................. 58 usart asynchronous master transmission.............. 69 usart asynchronous reception............................... 71 usart synchronous reception................................. 75 usart synchronous transmission............................ 73 wake-up from sleep via interrupt ............................. 98 timing diagrams and specifications................................. 124 a/d conversion......................................................... 138 brown-out reset (bor) ............................................ 126 capture/compare/pwm (ccp)................................. 128 clkout and i/o....................................................... 125 external clock........................................................... 124 i 2 c bus data ............................................................. 134 i 2 c bus start/stop bits ....................................... 134 oscillator start-up timer (ost)................................. 126 parallel slave port (psp).......................................... 129 power-up timer (pwrt)........................................... 126 reset ...................................................................... 126 timer0 and timer1.................................................... 127 usart synchronous receive (master/slave) ......... 136 usart synchronoustransmission (master/slave) .. 136 watchdog timer (wdt) ............................................ 126 tmr0 register.................................................................... 17 tmr1cs bit ........................................................................ 43 tmr1h register ................................................................. 17 tmr1l register.................................................................. 17 tmr1on bit ........................................................................ 43 tmr2 register.................................................................... 17 tmr2on bit ........................................................................ 47 to bit .................................................................................. 19 toutps0 bit....................................................................... 47 toutps1 bit....................................................................... 47 toutps2 bit....................................................................... 47 toutps3 bit....................................................................... 47 trisa register ............................................................. 18, 29 trisb register ............................................................. 18, 31 trisc register............................................................. 18, 33 trisd register............................................................. 18, 34 trise register ....................................................... 18, 35, 36 txsta register .................................................................. 65 u ua....................................................................................... 56 universal synchronous asynchronous receiver transmitter (usart) .......................................................... 65 update address bit, ua ...................................................... 56 usart asynchronous mode................................................... 68 asynchronous receiver.............................................. 70 asynchronous reception............................................ 71 asynchronous transmitter.......................................... 68 baud rate generator (brg) ...................................... 67 receive block diagram .............................................. 70 sampling..................................................................... 67 synchronous master mode......................................... 72 timing diagram, synchronous receive ........... 136 timing diagram, synchronous transmission... 136 synchronous master reception ................................. 74 synchronous master transmission ............................ 72 synchronous slave mode........................................... 76 synchronous slave reception ................................... 76 synchronous slave transmit...................................... 76 transmit block diagram ............................................. 68 uv erasable devices............................................................ 7 w wake-up from sleep......................................................... 97 watchdog timer (wdt).................................... 85, 87, 90, 95 timing diagram ........................................................ 126 wcol ................................................................................. 57 wdt ................................................................................... 90 block diagram ............................................................ 96 period ......................................................................... 95 programming considerations ..................................... 96 time-out...................................................................... 91 wr pin ................................................................................ 37 write collision detect bit, wcol........................................ 57 www, on-line support ..................... .................................. 3 z z bit..................................................................................... 19
pic16c63a/65b/73b/74b ds30605d-page 174 ? 1998-2013 microchip technology inc. notes:
? 1998-2013 microchip technology inc. ds30605d-page 175 the microchip web site microchip provides online support via our www site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchip?s customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com . under ?support?, click on ?customer change notification? and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://microchip.com/support
ds30605d-page 176 ? 1998-2013 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip product. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this document. to: technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds30605d 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document?
? 1998-2013 microchip technology inc. ds30605d-page 177 pic16c63a/65b/73b/74b product identification system to order or obtain information, e.g. , on pricing or delivery, refer to the factory or the listed sales office. * jw devices are uv erasable and can be programmed to any device c onfiguration. jw devices meet the electrical requirement of each oscillator type (including lc devices). sales and support part no. -xx x /xx xxx pattern package temperature range frequency range device device pic16c6x (1) , pic16c6xt (2) ; v dd range 4.0v to 5.5v pic16lc6x (1) , pic16lc6xt (2) ; v dd range 2.5v to 5.5v pic16c7x (1) , pic16c7xt (2) ; v dd range 4.0v to 5.5v pic16lc7x (1) , pic16lc7xt (2) ; v dd range 2.5v to 5.5v frequency range 04 = 4 mhz 20 = 20 mhz temperature range blank = 0c to 70c (commercial) i = -40c to +85c (industrial) e = -40c to +125c (extended) package jw = windowed cerdip pq = mqfp (metric pqfp) pt = tqfp (thin quad flatpack) so = soic sp = skinny plastic dip p=pdip l=plcc ss = ssop pattern qtp, sqtp, code or special requirements (blank otherwise) examples: a) pic16c74b -04/p 301 = commercial temp., pdip package, 4 mhz, normal v dd limits, qtp pattern #301. b) pic16lc63a - 04i/so = industrial temp., soic package, 200 khz, extended v dd limits. c) pic16c65b - 20i/p = industrial temp., pdip package, 20 mhz, normal v dd limits. note 1: c = cmos lc = low power cmos 2: t = in tape and reel - soic, ssop, plcc, qfp, tq and fp packages only. data sheets products supported by a preliminary data sheet may have an e rrata sheet describing minor operational differences and recom- mended workarounds. to determine if an erra ta sheet exists for a particular device, please contact one of the following: 1. your local microchip sales office 2. the microchip worldwide site (www.microchip.com)
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? 1998-2013 microchip technology inc. ds30605d-page 185 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, flashflex, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mtp, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. analog-for-the-digital age, app lication maestro, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mpf, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, sqi, serial quad i/o, total endurance, tsharc, uniwindriver, wiperlock, zena and z-scale are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. gestic and ulpp are registered trademarks of microchip technology germany ii gmbh & co. & kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 1998-2013, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 9781620769324 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 ==
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